Jacob Davyd Smith

US Patent:

7364991, Apr 29, 2008

Filed:

Apr 27, 2006

Appl. No.:

11/414012

Inventors:

David Bour - Cupertino CA, US
Jacob Smith - Santa Clara CA, US
Sandeep Nijhawan - Los Altos CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/20
H01L 21/36
H01L 31/20

US Classification:

438483, 438486

Abstract:

Methods are disclosed for fabricating a compound nitride semiconductor structure. An amorphous buffer layer that includes nitrogen and a group-III element is formed over a substrate disposed within a substrate processing chamber at a first temperature. The temperature within the chamber is increased to a second temperature at which the amorphous buffer layer coalesces into crystallites over the substrate. The substrate is exposed to a corrosive agent to destroy at least some of the crystallites. A crystalline nitride layer is formed over the substrate at a third temperature using the crystallites remaining after exposure to the corrosive agent as seed crystals. The third temperature is greater than the first temperature. The crystalline nitride layer also includes nitrogen and a group-III element.

US Patent:

7374960, May 20, 2008

Filed:

Aug 23, 2006

Appl. No.:

11/508523

Inventors:

David Bour - Cupertino CA, US
Sandeep Nijhawan - Los Altos CA, US
Lori D. Washington - Union City CA, US
Jacob W. Smith - Santa Clara CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/00

US Classification:

438 46, 438 47, 438 77, 438 82, 438 99, 257E21108, 257E21126

Abstract:

Methods and systems are provided of fabricating a compound nitride semiconductor structure. A substrate is disposed within a processing chamber into which a group-III precursor and a nitrogen precursor are flowed. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process using the precursors. The substrate is transferred to a transfer chamber where a temperature and a curvature of the layer are measured. The substrate is then transferred to a second processing chamber where a second layer is deposited.

US Patent:

7399653, Jul 15, 2008

Filed:

Apr 28, 2006

Appl. No.:

11/414581

Inventors:

David Bour - Cupertino CA, US
Jacob Smith - Santa Clara CA, US
Jie Su - Santa Clara CA, US
Sandeep Nijhawan - Los Altos CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/00

US Classification:

438 46, 438478, 438479

Abstract:

Nitride optoelectronic devices that have asymmetric double-sided structures and methods fabricating such structures are disclosed. Two n-type III-N layers are formed simultaneously over opposite sides of a substrate with substantially the same composition. Thereafter, a p-type III-N active layer is formed over one of the n-type III-N layers but not over the other.

US Patent:

7416995, Aug 26, 2008

Filed:

Nov 12, 2005

Appl. No.:

11/273381

Inventors:

R. Suryanarayanan Iyer - St. Paul MN, US
Sanjeev Tandon - Sunnyvale CA, US
Jacob W. Smith - Santa Clara CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/31

US Classification:

438763, 438758, 257E21033

Abstract:

A method for fabricating a multiple layer silicon nitride film on a semiconductor substrate is provided herein. In one embodiment, a method for fabricating a multiple layer silicon nitride film on a semiconductor substrate includes providing a substrate over which the multiple layer silicon nitride film is to be formed; and forming the multiple layer silicon nitride film in a single processing reactor by: (a) depositing a base layer comprising silicon nitride on the base structure; (b) depositing a middle layer comprising a stress-controlling material on the base layer; and (c) depositing a top layer comprising silicon nitride on the middle layer. The stress-controlling material selectively increases or reduces the stress of the multiple layer silicon nitride film as compared to silicon nitride alone.

US Patent:

7459380, Dec 2, 2008

Filed:

May 5, 2006

Appl. No.:

11/418642

Inventors:

David Bour - Cupertino CA, US
Jacob Smith - Santa Clara CA, US
Lori Washington - Union City CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/20
H01L 21/36

US Classification:

438478, 438 41, 438 44, 438481, 257E21461, 257E21476, 257E21562

Abstract:

In accordance with the present invention, improved methods for reducing the dislocation density of nitride epitaxial films are provided. Specifically, an in-situ etch treatment is provided to preferentially etch the dislocations of the nitride epitaxial layer to prevent threading of the dislocations through the nitride epitaxial layer. Subsequent to etching of the dislocations, an epitaxial layer overgrowth is performed. In certain embodiments, the etching of the dislocations occurs simultaneously with growth of the epitaxial layer. In other embodiments, a dielectric mask is deposited within the etch pits formed at the dislocations prior to the epitaxial layer overgrowth.

US Patent:

7470599, Dec 30, 2008

Filed:

Apr 14, 2006

Appl. No.:

11/404390

Inventors:

Sandeep Nijhawan - Los Altos CA, US
David Eaglesham - Livermore CA, US
Lori Washington - Union City CA, US
David Bour - Cupertino CA, US
Jacob Smith - Santa Clara CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/30
H01L 21/46

US Classification:

438457

Abstract:

Methods are provided of fabricating a nitride semiconductor structure. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over one side of the substrate with a thermal chemical-vapor-deposition process. A second layer is similarly deposited over an opposite side of the substrate using the group-III precursor and the nitrogen precursor. The substrate is cooled after depositing the first and second layers without substantially deforming a shape of the substrate.

US Patent:

7488690, Feb 10, 2009

Filed:

Jul 6, 2004

Appl. No.:

10/885969

Inventors:

R. Suryanarayanan Iyer - Santa Clara CA, US
Andrew M. Lam - San Francisco CA, US
Yuji Maeda - Chiba, JP
Thomas Mele - Livermore CA, US
Jacob W. Smith - Santa Clara CA, US
Sean M. Seutter - San Jose CA, US
Sanjeev Tandon - Sunnyvale CA, US
Randhir P. Singh Thakur - San Jose CA, US
Sunderraj Thirupapuliyur - Sunnyvale CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/302
H01L 21/461
H01L 21/425
H01L 21/336

US Classification:

438724, 438257, 438710, 438514

Abstract:

An assembly comprises a multilayer nitride stack having nitride etch stop layers formed on top of one another, each of the nitride etch stop layers is formed using a film forming process. A method of making the multilayer nitride stack includes placing a substrate in a single wafer deposition chamber and thermally shocking the substrate momentarily prior to deposition. A first nitride etch stop layer is deposited over the substrate. A second nitride etch stop layer is deposited over the first nitride etch stop layer.

US Patent:

7560364, Jul 14, 2009

Filed:

May 5, 2006

Appl. No.:

11/429084

Inventors:

David Bour - Cupertino CA, US
Sandeep Nijhawan - Los Altos CA, US
Jacob Smith - Santa Clara CA, US
Lori Washington - Union City CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/20

US Classification:

438481, 257E2109, 257E21133, 257E21158, 257E21134, 257E21461, 438 41, 438341, 438117

Abstract:

In accordance with the present invention, improved methods for reducing the dislocation density of nitride epitaxial films are provided. Specifically, an in-situ etch treatment is provided to preferentially etch the dislocations of the nitride epitaxial layer to prevent threading of the dislocations through the nitride epitaxial layer. Subsequent to etching of the dislocations, an epitaxial layer overgrowth is performed. In certain embodiments, the etching of the dislocations occurs simultaneously with growth of the epitaxial layer. In other embodiments, a dielectric mask is deposited within the etch pits formed at the dislocations prior to the epitaxial layer overgrowth.