Jacob J White

US Patent:

6493849, Dec 10, 2002

Filed:

Sep 5, 2000

Appl. No.:

09/654972

Inventors:

Ricardo Telichevesky - San Jose CA
Kenneth S. Kundert - Los Altos CA
Jacob K. White - Belmont MA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 4, 716 1

Abstract:

An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a shooting method to form a non-linear system of equations for initial conditions of the circuit that directly result in the periodic steady state response; 2) solving the non-linear system via a Newton iterative method, where each iteration of the Newton method involves solution of a respective linear system of equations; and 3) for each iteration of the Newton method, solving the respective linear system of equations associated with the iteration of the Newton method via an iterative technique. The iterative technique may be a matrix-implicit application of a Krylov subspace technique, resulting in a computational cost that grows approximately in a linear fashion with the number of nodes in the circuit.

US Patent:

6636839, Oct 21, 2003

Filed:

Sep 5, 2000

Appl. No.:

09/654685

Inventors:

Ricardo Telichevesky - San Jose CA
Kenneth S. Kundert - Los Altos CA
Jacob K. White - Belmont MA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

706 1, 703 4

Abstract:

An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a shooting method to form a non-linear system of equations for initial conditions of the circuit that directly result in the periodic steady state response; 2) solving the non-linear system via a Newton iterative method, where each iteration of the Newton method involves solution of a respective linear system of equations; and 3) for each iteration of the Newton method, solving the respective linear system of equations associated with the iteration of the Newton method via an iterative technique. The iterative technique may be a matrix-implicit application of a Krylov subspace technique, resulting in a computational cost that grows approximately in a linear fashion with the number of nodes in the circuit.

US Patent:

60885238, Jul 11, 2000

Filed:

Nov 20, 1996

Appl. No.:

8/752812

Inventors:

Keith Shelton Nabors - Sunnyvale CA
Tze-Ting Fang - Palo Alto CA
Jacob Keaton White - Belmont MA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1560

US Classification:

39550035

Abstract:

A method and apparatus for making electrical circuits having RLCG lines is disclosed. The method depicts a circuit element taper of a selected element type as dependent upon an accumulated circuit element quantity. The method matches projections of the circuit element taper with projections of an approximate taper. The approximate taper depends upon the accumulated circuit element quantity. At least one reduced quantity for circuit element quantities of the selected element type is obtained on the computer. The one reduced quantity can be arranged in a reduced RLCG line having approximately the same performance as the RLCG line. The present invention should be particularly useful in verifying timing specifications and during the making of integrated circuits.

US Patent:

61516988, Nov 21, 2000

Filed:

Apr 28, 1997

Appl. No.:

8/847884

Inventors:

Ricardo Telichevesky - San Jose CA
Kenneth S. Kundert - Los Altos CA
Jacob K. White - Belmont MA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 1

Abstract:

An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a shooting method to form a non-linear system of equations for initial conditions of the circuit that directly result in the periodic steady state response; 2) solving the non-linear system via a Newton iterative method, where each iteration of the Newton method involves solution of a respective linear system of equations; and 3) for each iteration of the Newton method, solving the respective linear system of equations associated with the iteration of the Newton method via an iterative technique. The iterative technique may be a matrix-implicit application of a Krylov subspace technique, resulting in a computational cost that grows approximately in a linear fashion with the number of nodes in the circuit.

US Patent:

53351916, Aug 2, 1994

Filed:

Mar 27, 1992

Appl. No.:

7/859057

Inventors:

Kenneth S. Kundert - Belmont CA
Jacob K. White - Arlington MA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06G 763

US Classification:

364578

Abstract:

An apparatus and method for improved efficiency of operation of a circuit simulator. The simulation engine processor sends signals via flag registers to the component model processors to indicate which type of response is required from each component model. The component model processors send back only the requested response, thus minimizing processing time by avoiding generating response types that are not needed. Flexibility is enhanced by centralizing tasks in the simulation engine rather than in the component models, in order to facilitate experimentation and variation in circuit configurations without extensive modifications of component model design.

US Patent:

52610632, Nov 9, 1993

Filed:

Dec 7, 1990

Appl. No.:

7/624438

Inventors:

Jack W. Kohn - San Jose CA
Jacob White - Arlington MA

Assignee:

IBM Corp. - Armonk NY

International Classification:

G06F 938

US Classification:

395375

Abstract:

A pipeline data processor is simultaneously operable in a pipeline mode, a parallel mode and a vector mode which is a special case of the pipeline mode. Each pipeline stage has its own stage program counter. A global program counter is incremented in the pipeline mode. The instruction addresses generated in the global program counter are distributed to those pipeline stages which first become available to perform pipelined data processing. Any given pipeline stage may dynamically switch between pipeline mode and a parallel mode in which the stage program counter counts and supplies instruction addresses independently of any other pipeline stage. A vector mode uses pipeline instructions which are repeated to enable any number of the pipeline stages to participate in vector calculations. In the vector mode, one pipeline instruction address is held in the global program counter to be repeatedly supplied to respective first available pipeline stages until the vector calculations are completed. Other program means are disclosed which effect efficient control of program executions in all three modes and enable the concurrent execution in any mode by any of the pipeline stages.