Jae Hyung Cho

US Patent:

7235412, Jun 26, 2007

Filed:

May 11, 2004

Appl. No.:

10/842770

Inventors:

Mohsen Hossein Mardi - Fremont CA, US
Jae Cho - Saratoga CA, US
Xin X. Wu - Fremont CA, US
Chih-Chung Wu - Hsinchu, TW
Shih-Liang Liang - Chung Li, TW
Sanjiv Stokes - Los Altos CA, US
Hassan K. Bazargan - San Jose CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H01L 21/66

US Classification:

438 14, 438 15, 438 18

Abstract:

A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.