Jae Y Choi

US Patent:

20120150523, Jun 14, 2012

Filed:

Feb 23, 2012

Appl. No.:

13/403594

Inventors:

Jae Young Choi - Atlanta GA, US
Madhavan Swaminathan - Marietta GA, US

Assignee:

GEORGIA TECH RESEARCH CORPORATION - Atlanta GA

International Classification:

G06F 17/50

US Classification:

703 14

Abstract:

In a method of simulating electrical characteristics of a circuit board having a plurality of features, the plurality of features is projected onto a planar construct. A Delaunay triangulation routine for generating a triangular mesh that corresponds to the single planar construct is executed on the digital computer. A routine that generates a Voronoi diagram corresponding to the triangular mesh. An equivalent circuit for each triangle is determined. The equivalent circuit includes exactly three sub-circuits that couple a vertex within the triangle to a vertex within an adjacent triangle and exactly one sub-circuit that couples the vertex within the triangle to a reference plane. A routine solves, for each triangle, an equation describing an electrical characteristic value based on the equivalent circuit corresponding to the triangle. A routine for generating a human-perceptible indication of the electrical characteristic value for each triangle is executed on the digital computer.