Jamal Riani

US Patent:

8276052, Sep 25, 2012

Filed:

Jan 20, 2010

Appl. No.:

12/690829

Inventors:

Jamal Riani - Santa Clara CA, US
Haoli Qian - Fremont CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 13/03
H03M 13/00
G01R 31/28
H04L 27/08
H04L 12/26
H04B 17/00

US Classification:

714794, 714775, 714795, 714821, 714739, 375341, 370216, 370242, 4552261

Abstract:

A system and method for recovering the seed of a pseudo-random binary sequence (PRBS) using soft decisions is disclosed. In some implementations, a log-likelihood ratio is calculated to determine the certainty with which each bit in the seed has been recovered, and in some implementations, the value of the PRBS is used in the calculation of the log-likelihood ratio. In some implementations, a linear feedback shift register stores the log-likelihood ratio for each bit in the sequence.

US Patent:

8489970, Jul 16, 2013

Filed:

Sep 13, 2012

Appl. No.:

13/614397

Inventors:

Jamal Riani - Santa Clara CA, US
Haoli Qian - Fremont CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 13/03
H03M 13/00
G01R 31/28
H04L 27/08
H04L 12/26
H04B 17/00

US Classification:

714794, 714775, 714795, 714821, 714739, 375341, 370216, 370242, 4552261

Abstract:

A receiver includes a seed recovery module and a pseudo-random binary sequence generator. The seed recovery module is configured to receive a pseudo-random binary sequence and a signal including a seed value, recover the seed value from the signal using the pseudo-random binary sequence, and determine a likelihood that a bit of the seed value was recovered accurately. The pseudo-random binary sequence generator is configured to generate the pseudo-random binary sequence, and adjust the pseudo-random binary sequence based on the likelihood until the likelihood is greater than a threshold.

US Patent:

8532203, Sep 10, 2013

Filed:

May 27, 2009

Appl. No.:

12/472588

Inventors:

Jamal Riani - Santa Clara CA, US
Runsheng He - Sunnyvale CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H04K 1/10
H04L 27/28

US Classification:

375260

Abstract:

Embodiments of the present invention include communication systems and methods using channel estimation based on cumulants. In one embodiment, the present invention includes a receiver comprising a sampler coupled to a communication channel for receiving an input signal and providing samples of the input signal at a first sample rate, a channel estimation circuit coupled to receive the sampled input signal, the channel estimation circuit estimating the amplitude response of the communication channel by autocorrelating the input signal, estimating the phase response of the communication channel using a fourth order cumulant of the input signal, and generating an estimated impulse response of the communication channel using the estimated amplitude response and the estimated phase response, and a channel initialization circuit coupled to the channel estimation circuit for configuring the receiver using the estimated impulse response.

US Patent:

8644372, Feb 4, 2014

Filed:

Apr 27, 2012

Appl. No.:

13/459049

Inventors:

Jamal Riani - Fremont CA, US
Jagadish Venkataraman - Santa Clara CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03H 7/30
H03H 7/40
H03K 5/159

US Classification:

375233

Abstract:

In a method for detecting symbols in a signal received via a communication channel, the signal including a plurality of signal points, each signal point in the plurality of signal points is processed using a decision feedback equalizer (DFE) to produce a DFE decision. Reliability of the DFE decision is assessed to determine whether the DFE decision is at least one of i) reliable or ii) not reliable. When it is determined that the DFE decision is not reliable, a block of signal points of the plurality of signal points is processed using a Viterbi Detector (VD) to generate a block of VD decisions. The block of VD decisions is selected to be used in place of a block of DFE decisions.

US Patent:

7987396, Jul 26, 2011

Filed:

Sep 9, 2009

Appl. No.:

12/556483

Inventors:

Jamal Riani - Santa Clara CA, US
Haoli Qian - Fremont CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 11/00

US Classification:

714704, 714709

Abstract:

The present specification describes techniques and apparatus that adjust filter tap values to be used in filtering a data value input to a detector and/or that increase or decrease a threshold value used to determine whether to adjust the filter tap values.

US Patent:

20220376712, Nov 24, 2022

Filed:

May 31, 2022

Appl. No.:

17/828850

Inventors:

- Singapore, SG
Jamal RIANI - Fremont CA, US

International Classification:

H03M 13/45
H03M 13/37
H03M 13/11
H03M 13/00
H03M 13/25

Abstract:

The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.

US Patent:

20220302930, Sep 22, 2022

Filed:

Jun 6, 2022

Appl. No.:

17/832785

Inventors:

- Singapore, SG
Volodymyr SHVYDUN - Los Altos CA, US
Jamal RIANI - Fremont CA, US
Ilya LYUBOMIRSKY - Santa Clara CA, US

International Classification:

H03M 13/27
H03M 13/15

Abstract:

A communication device includes interleaver circuitry that receives, from a host device, a first encoded data stream comprised of a plurality of symbols encoded with a first type of error correction code and interleaves the plurality of symbols of the first encoded data stream into symbol sections each including a predetermined number of symbols encoded with the first type of error correction code. Encoder circuitry encodes the first encoded data stream in accordance with a second type of error correction code different from the first type of error correction code by generating, for each of the symbol sections, an error code block corresponding to the symbols in the symbol section and outputs a second encoded data stream including the first encoded data stream and the error code block.

US Patent:

20220190836, Jun 16, 2022

Filed:

Jan 3, 2022

Appl. No.:

17/567588

Inventors:

- Singapore, SG
Jorge PERNILLO - Daly City CA, US
Junyi SUN - Singapore, SG
Praveen PRABHA - Lake Forest CA, US
Chang-Feng LOI - Singapore, SG
Yu LIAO - Longmont CO, US
Jamal RIANI - Fremont CA, US
Belal HELAL - Santa Clara CA, US
Karthik S. GOPALAKRISHNAN - Cupertino CA, US
Aaron BUCHWALD - Newport Beach CA, US

International Classification:

H03L 7/197
H04L 7/033
H03L 7/099
H03L 7/087
H03L 7/08

Abstract:

The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.