James T Ballard

US Patent:

20200258988, Aug 13, 2020

Filed:

Apr 27, 2020

Appl. No.:

16/859154

Inventors:

- Singapore, SG
George Imthurn - San Diego CA, US
James Douglas Ballard - Solana Beach CA, US
Yashodhan Vijay Moghe - Hobart, AU

Assignee:

Silanna Asia Pte Ltd - Singapore

International Classification:

H01L 29/40
H01L 29/66
H01L 29/78
G01R 19/00

Abstract:

An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.

US Patent:

20190148544, May 16, 2019

Filed:

Dec 28, 2018

Appl. No.:

16/234864

Inventors:

- Singapore, SG
James Douglas Ballard - Solana Beach CA, US
Yashodhan Vijay Moghe - Marsfield, NSW 2122, AU

International Classification:

H01L 29/78
G01R 19/00
H01L 29/40
H01L 29/66

Abstract:

An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.

US Patent:

20170162658, Jun 8, 2017

Filed:

Jan 16, 2017

Appl. No.:

15/407174

Inventors:

- Singapore, SG
James Douglas Ballard - Solana Beach CA, US
Yashodhan Vijay Moghe - Marsfield, AU

Assignee:

Silanna Asia Pte Ltd - Singapore

International Classification:

H01L 29/40
G01R 19/00
H01L 29/78

Abstract:

An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.