Medical Center AnesthesiolgstMedical Center Anesthesiologists 1111 6 Ave, Des Moines, IA 50314 5152830463 (phone), 5152830794 (fax)
Education:
Medical School University of Iowa Carver College of Medicine Graduated: 1984
Languages:
English Spanish
Description:
Dr. Bartlett graduated from the University of Iowa Carver College of Medicine in 1984. He works in Des Moines, IA and specializes in Anesthesiology. Dr. Bartlett is affiliated with Mercy Medical Center & Childrens Hospital Des Moines.
TeamHealth 301 N Alexander St, Plant City, FL 33563 8137571200 (phone), 8137578423 (fax)
Education:
Medical School University of Utah School of Medicine Graduated: 2008
Languages:
English
Description:
Dr. Bartlett graduated from the University of Utah School of Medicine in 2008. He works in Plant City, FL and specializes in Emergency Medicine. Dr. Bartlett is affiliated with South Florida Baptist Hospital.
Michael C. Greim - Garland TX James R. Bartlett - Plano TX
Assignee:
Intelect communications, Inc. - Richardson TX
International Classification:
G06F 1200
US Classification:
711147, 711148, 711152, 711163
Abstract:
A multi-processor system includes a global bus ( ) having associated therewith a global address space with a plurality of processor nodes ( ) associated therewith. Each of the processor nodes ( ) has a CPU ( ) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. The global bus ( ) has associated therewith an arbiter ( ). Each of the processing nodes interfaces with a global register ( ) which is operable to contain paging registers for each of the files. A portion of the memory space in the processing nodes is paged over to the global address space. To facilitate the upper address bits of the global address space they are stored in a paging register and then the arbiter ( ) selects these upper address bits for output to the bus. The lower address bits are provided by the particular processor node that is accessing the global address space.
Michael C. Greim - Garland TX James R. Bartlett - Plano TX
Assignee:
Intelect Communications, Inc. - Richardson TX
International Classification:
H04J 316
US Classification:
370466
Abstract:
A multi-processor system includes a global bus ( ) with a global address space and a plurality of processor nodes ( ). Each of the processor nodes ( ) has a CPU ( ) interfaced with a local bus having a local address space. A dual port SRAM (DPSRAM) ( ) is provided for interfacing between the global bus ( ) and the local bus ( ). Each DPSRAM ( ) for each processor core ( ) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node ( ), it is only necessary to address the designated DPSRAM ( ) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU ( ) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM ( ). This results in only a single access cycle for data transfer. Each of the CPUs ( ) can communicate directly with another of the CPUs ( ) through an interprocessor communication network.
Michael C. Greim - Garland TX James R. Bartlett - Plano TX
Assignee:
Terraforce Technologies Corp. - Richardson TX
International Classification:
G06F 1200
US Classification:
711148, 711149, 711153, 710305
Abstract:
A multi-processor system includes a global bus ( ) having associated therewith a global address space with a plurality of processor nodes ( ) associated therewith. Each of the processor nodes ( ) has a CPU ( ) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. A dual port SRAM (DPSRAM)( ) is provided for interfacing between the global bus ( ) and the local bus ( ). Each DPSRAM ( ) for each processor core ( ) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node ( ), it is only necessary to address the designated DPSRAM ( ) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU ( ) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM ( ). This results in only a single access cycle for transfer of the block of data from the global resources to the designated CPU ( ).
Multi-Processor Architecture For Parallel Signal And Image Processing
Winthrop W. Smith - Richardson TX James R. Bartlett - Plano TX Jay T. Labhart - Allen TX
Assignee:
Tera Force Technology Corp. - Richardson TX
International Classification:
G06F 1300
US Classification:
710100, 709215, 711150
Abstract:
A quad-processor arrangement having 6 communications paths, one path between each of every possible pair of processors. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processors local memory to another processors local memory, such as commonly done during signal processing corner turning operations. The communications paths are controlled and interfaced to the processors through field programmable logic, which allows the board to be configured both statically and dynamically to optimize the data transfer characteristics of the module to match the requirements of the application software. The programmable logic may be configured so that the module emulates other existing board architectures in order to support legacy applications.
Switchable Multi-Channel Data Transcoding And Transrating System
Pawan Jaggi - Plano TX, US Mark Daniel Fears - Plano TX, US Paul Byron Banta - Plano TX, US Xiaohui Wei - Plano TX, US James Richard Bartlett - Plano TX, US
International Classification:
H04N 21/234
US Classification:
725109
Abstract:
A video transport stream over IP (TS/IP) server system comprises a set of video server blocks. A video server block comprises a pair of codecs and a primary FPGA, the codecs based on a fully programmable high speed DSP processor. The video server block further comprises a pair of VioIP engines for translating transport streams into IP packet streams. The video TS/IP server can perform transcoding, transrating and statistical multiplexing functions between ingress and egress transport streams. The video TS/IP server can ingress or egress HD-SDI and DVB-ASI data streams to or from an IP network via TS/IP. A host subsystem is embedded in a stand-alone embodiment. Multiple video TS/IP servers can be hosted by a PC in a PC host embodiment.
Dsp Interrupt Control For Handling Multiple Interrupts
Michael C. Greim - Garland TX James R. Bartlett - Plano TX
Assignee:
Intelect Systems Corporation
International Classification:
G06F 1324
US Classification:
710260
Abstract:
A multi-processor system is provided having a processor array configured of a plurality of CPUs (20) that are disposed on a global bus (14). A VEM interface (18) is provided for interfacing between the global bus (14) and a system bus (12). Interrupts that are generated on the system bus (12) are mapped to the CPUs (20) through an interrupt controller (82). The interrupt controller (82) is operable to receive multiple interrupts and store these interrupts and their associated interrupt vectors. After storage, a gating register associated with each CPU (20) is examined to determine which interrupts are serviced by a particular CPU (20). If an interrupt is received that is to be serviced by one or more of the CPUs (20), then an external interrupt is generated for that CPU (20). Once the external interrupt is generated, the CPU will then examine a flag register associated therewith, which flag bits are set only if the interrupt controller (82) has determined that the CPU (20) is to receive the interrupt in accordance with the contents of the gating registers. The CPU (20) will then service the particular interrupts directed thereto by accessing the stored interrupt vectors.
analyzing the data, and it's expected that more insights about the origin and nature of our universe will be published next year. "The kind of questions we ask now we never would have thought possible to even ask decades ago, long before Planck," said James Bartlett, a US Planck team member from JPL.
Date: Feb 05, 2015
Source: Google
Gotham Awards: Benh Zeitlin Wins Breakthrough Director
The winner of the Best Film Not Playing at a Theater Near You Award went to An Oversimplication of Her Beauty, directed by Terence Nance and produced by Nance, Andrew Corkin and James Bartlett. The film tells the love story between two young African Americans.
"Planck is helping to reveal hidden material between galaxy clusters that we couldn't see clearly before," said James Bartlett of NASA's Jet Propulsion Laboratory, Pasadena, Calif., a member of the U.S. Planck science team. Planck is a European Space Agency mission with significant participati
Date: Nov 21, 2012
Category: Sci/Tech
Source: Google
Youtube
James Bartlett & Lauren Jones - 1st place Adv...
Chapters: 00:00 Intro If you wanna join the Midland Swing Open next ...
Duration:
4m 7s
James Bartlett & Lauren Jones - 1st place Str...
Chapters: 00:00 Intro If you wanna join the Midland Swing Open next ...
Duration:
2m 57s
Sir Andrs Schiff Piano Masterclass at the RCM...
On Sunday 10 April 2016 the Royal College of Music welcomed back Sir A...
Duration:
58m 40s
James Bartlett & Kalina Kwiatkowska - All-Sta...
Chapters: 00:00 Intro 00:27 1st song - slow 02:09 2nd song -fast If ...
Duration:
4m 26s
Midland Swing Open Dance Competition - James ...
Midland Swing Open Dance Competition - James Bartlett & Lauren Jones -...
Duration:
2m 11s
James Bartlett & Alesya Kovaleva King Swing 2...
West Coast Swing Song: Demons - Imagine Dragons (Cover by Jasmine Thom...