James Neil Bartlett

US Patent:

6393530, May 21, 2002

Filed:

Apr 17, 1998

Appl. No.:

09/062030

Inventors:

Michael C. Greim - Garland TX
James R. Bartlett - Plano TX

Assignee:

Intelect communications, Inc. - Richardson TX

International Classification:

G06F 1200

US Classification:

711147, 711148, 711152, 711163

Abstract:

A multi-processor system includes a global bus ( ) having associated therewith a global address space with a plurality of processor nodes ( ) associated therewith. Each of the processor nodes ( ) has a CPU ( ) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. The global bus ( ) has associated therewith an arbiter ( ). Each of the processing nodes interfaces with a global register ( ) which is operable to contain paging registers for each of the files. A portion of the memory space in the processing nodes is paged over to the global address space. To facilitate the upper address bits of the global address space they are stored in a paging register and then the arbiter ( ) selects these upper address bits for output to the bus. The lower address bits are provided by the particular processor node that is accessing the global address space.

US Patent:

6446086, Sep 3, 2002

Filed:

Jun 30, 1999

Appl. No.:

09/345699

Inventors:

James Bartlett - Arlington TX
John Kerulis - Little Elm TX
Robert Ngan - Chicago IL
Jay Rasmussen - Coppell TX
Brian Rittenhouse - Frisco TX

Assignee:

Computer Sciences Corporation - Austin TX

International Classification:

G06F 1730

US Classification:

707200

Abstract:

An improved method and system for logging transaction records in a computer system. The method may include writing a confirmation log record to the log file for a transaction that completes normally, and not writing a confirmation log record for transactions that are aborted. The log file may be unloaded periodically by an unload program. The unload program may write transaction log records accompanied by a confirmation log record to a good output file and transaction log records not accompanied by a confirmation log record to a suspended output file. On a subsequent execution, the unload program may combine the log records in the log file and the suspended file. The unload program may write transaction log records accompanied by a confirmation log record to a good output file. The unload program may write transaction log records not accompanied by a confirmation log record and which have not exceeded a transaction time limit to a suspended output file. The unload program may write transaction log records not accompanied by a confirmation log record and which have exceeded a transaction time limit to a disposal output file.

US Patent:

6456628, Sep 24, 2002

Filed:

Jul 17, 1998

Appl. No.:

09/118176

Inventors:

Michael C. Greim - Garland TX
James R. Bartlett - Plano TX

Assignee:

Intelect Communications, Inc. - Richardson TX

International Classification:

H04J 316

US Classification:

370466

Abstract:

A multi-processor system includes a global bus ( ) with a global address space and a plurality of processor nodes ( ). Each of the processor nodes ( ) has a CPU ( ) interfaced with a local bus having a local address space. A dual port SRAM (DPSRAM) ( ) is provided for interfacing between the global bus ( ) and the local bus ( ). Each DPSRAM ( ) for each processor core ( ) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node ( ), it is only necessary to address the designated DPSRAM ( ) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU ( ) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM ( ). This results in only a single access cycle for data transfer. Each of the CPUs ( ) can communicate directly with another of the CPUs ( ) through an interprocessor communication network.

US Patent:

6678801, Jan 13, 2004

Filed:

Apr 17, 1998

Appl. No.:

09/062146

Inventors:

Michael C. Greim - Garland TX
James R. Bartlett - Plano TX

Assignee:

Terraforce Technologies Corp. - Richardson TX

International Classification:

G06F 1200

US Classification:

711148, 711149, 711153, 710305

Abstract:

A multi-processor system includes a global bus ( ) having associated therewith a global address space with a plurality of processor nodes ( ) associated therewith. Each of the processor nodes ( ) has a CPU ( ) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. A dual port SRAM (DPSRAM)( ) is provided for interfacing between the global bus ( ) and the local bus ( ). Each DPSRAM ( ) for each processor core ( ) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node ( ), it is only necessary to address the designated DPSRAM ( ) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU ( ) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM ( ). This results in only a single access cycle for transfer of the block of data from the global resources to the designated CPU ( ).

US Patent:

6757761, Jun 29, 2004

Filed:

May 8, 2001

Appl. No.:

09/850939

Inventors:

Winthrop W. Smith - Richardson TX
James R. Bartlett - Plano TX
Jay T. Labhart - Allen TX

Assignee:

Tera Force Technology Corp. - Richardson TX

International Classification:

G06F 1300

US Classification:

710100, 709215, 711150

Abstract:

A quad-processor arrangement having 6 communications paths, one path between each of every possible pair of processors. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processors local memory to another processors local memory, such as commonly done during signal processing corner turning operations. The communications paths are controlled and interfaced to the processors through field programmable logic, which allows the board to be configured both statically and dynamically to optimize the data transfer characteristics of the module to match the requirements of the application software. The programmable logic may be configured so that the module emulates other existing board architectures in order to support legacy applications.

US Patent:

6952741, Oct 4, 2005

Filed:

Jun 30, 1999

Appl. No.:

09/345698

Inventors:

James Bartlett - Arlington TX, US
John Kerulis - Little Elm TX, US
Robert Ngan - Chicago IL, US
Jay Rasmussen - Coppell TX, US
Brian Rittenhouse - Frisco TX, US

Assignee:

Computer Sciences Corporation - Austin TX

International Classification:

G06F015/16
G06F012/00

US Classification:

709245, 709248, 711100, 711118, 711154

Abstract:

An improved synchronization system and method for copies of data in a computer system. The computer system comprises a cluster, wherein each computer in the cluster may store a local copy of a data set along with a validity flag for the local copy. The computer system further comprises a coupling system which is connected to each of the computers in the cluster through a coupling system interface program, wherein the coupling system is configured to coordinate the data sharing and workload of the cluster. The computer system also comprises an external data storage shared by the computers in the cluster. One of the computers may read a first copy of the data set from a primary data set on the external data storage. The computer may then store the first copy locally and set a first validity flag to indicate that the first copy is valid. Another computer, server, or application program may make a second copy of the primary data set and set a second validity flag to valid.

US Patent:

7130924, Oct 31, 2006

Filed:

Oct 4, 2005

Appl. No.:

11/243461

Inventors:

James Bartlett - Arlington TX, US
John Kerulis - Little Elm TX, US
Robert Ngan - Chicago IL, US
Jay Rasmussen - Coppell TX, US
Brian Rittenhouse - Frisco TX, US

Assignee:

Computer Sciences Corporation - Austin TX

International Classification:

G06F 15/16
G06F 12/00

US Classification:

709245, 711100, 711118, 711154, 709248

Abstract:

An improved synchronization system and method for copies of data in a computer system. The computer system comprises a cluster, wherein each computer in the cluster may store a local copy of a data set along with a validity flag for the local copy. The computer system further comprises a coupling system which is connected to each of the computers in the cluster through a coupling system interface program, wherein the coupling system is configured to coordinate the data sharing and workload of the cluster. The computer system also comprises an external data storage shared by the computers in the cluster. One of the computers may read a first copy of the data set from a primary data set on the external data storage. The computer may then store the first copy locally and set a first validity flag to indicate that the first copy is valid. Another computer, server, or application program may make a second copy of the primary data set and set a second validity flag to valid.

US Patent:

7581025, Aug 25, 2009

Filed:

Oct 31, 2006

Appl. No.:

11/590666

Inventors:

James Bartlett - Arlington TX, US
John Kerulis - Little Elm TX, US
Robert Ngan - Chicago IL, US
Jay Rasmussen - Coppell TX, US
Brian Rittenhouse - Frisco TX, US

Assignee:

Computer Sciences Corporation - El Segundo CA

International Classification:

G06F 15/16
G06F 12/00

US Classification:

709245, 711100, 711118, 711144, 711154, 709248

Abstract:

An improved synchronization system and method for copies of data in a computer system. The computer system comprises a cluster, wherein each computer in the cluster may store a local copy of a data set along with a validity flag for the local copy. The computer system further comprises a coupling system which is connected to each of the computers in the cluster through a coupling system interface program, wherein the coupling system is configured to coordinate the data sharing and workload of the cluster. The computer system also comprises an external data storage shared by the computers in the cluster. One of the computers may read a first copy of the data set from a primary data set on the external data storage. The computer may then store the first copy locally and set a first validity flag to indicate that the first copy is valid. Another computer, server, or application program may make a second copy of the primary data set and set a second validity flag to valid.

Address:

1801 Mccord Way APT 1212, Frisco, TX 75033

Phone:

9367773676

VIN:

YV1672MK4C2280134

Make:

VOLVO

Model:

C30

Year:

2012