James Abbott Bowman

US Patent:

7701459, Apr 20, 2010

Filed:

Nov 3, 2006

Appl. No.:

11/556525

Inventors:

Dane T. Mrazek - Redwood City CA, US
James C. Bowman - Pescadero CA, US
Sameer M. Gauria - Mountain View CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 15/80
G06T 17/00
G06F 13/00

US Classification:

345505, 345420, 345536

Abstract:

A graphics system has parallel processing units that do not share vertex information. The graphics system constructs independent batches of work for the parallel processing units in which each batch of work has a list of vertices for a set of primitives.

US Patent:

7755631, Jul 13, 2010

Filed:

Oct 24, 2006

Appl. No.:

11/552350

Inventors:

Dane T. Mrazek - Redwood City CA, US
Sameer M. Gauria - Mountain View CA, US
James C. Bowman - Pescadero CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 15/00

US Classification:

345501

Abstract:

Disclosed are an apparatus, a method, a programmable graphics processing unit (“GPU”), a computer device, and a computer medium to facilitate, among other things, the generation of parallel data streams to effect parallel processing in at least a portion of a graphics pipeline of a GPU. In one embodiment, an input of the apparatus receives graphics elements in a data stream of graphics elements. The graphics pipeline can use the graphics elements to form computer-generated images. The apparatus also can include a transposer configured to produce parallel attribute streams. Each of the parallel attribute streams includes a type of attribute common to the graphics elements. In one embodiment, the transposer can be configured to convert at least a portion of the graphics pipeline from a single data stream to multiple data streams (e. g. , executable by multiple threads of execution) while reducing the memory size requirements to implement such a conversion.

US Patent:

7796137, Sep 14, 2010

Filed:

Oct 24, 2006

Appl. No.:

11/552415

Inventors:

Dane T. Mrazek - Redwood City CA, US
Sameer M. Gauria - Mountain View CA, US
James C. Bowman - Pescadero CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G09G 5/36
G06F 12/08

US Classification:

345557, 711 3

Abstract:

Disclosed are an apparatus, a system, a method, a graphics processing unit (“GPU”), a computer device, and a computer medium to implement a pool of independent enhanced tags to, among other things, decouple a dependency between tags and cachelines. In one embodiment, an enhanced tag-based cache structure includes a tag repository configured to maintain a pool of enhanced tags. Each enhanced tag can have a match portion configured to form an association between the enhanced tag and an incoming address. Also, an enhanced tag can have a data locator portion configured to locate a cacheline in the cache in response to the formation of the association. The data locator portion enables the enhanced tag to locate multiple cachelines. Advantageously, the enhanced tag-based cache structure can be formed to adjust the degree of reusability of the enhanced tags independent from the degree of latency tolerance for the cacheline repository.