James E Bowman

US Patent:

7701459, Apr 20, 2010

Filed:

Nov 3, 2006

Appl. No.:

11/556525

Inventors:

Dane T. Mrazek - Redwood City CA, US
James C. Bowman - Pescadero CA, US
Sameer M. Gauria - Mountain View CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 15/80
G06T 17/00
G06F 13/00

US Classification:

345505, 345420, 345536

Abstract:

A graphics system has parallel processing units that do not share vertex information. The graphics system constructs independent batches of work for the parallel processing units in which each batch of work has a list of vertices for a set of primitives.

US Patent:

7755631, Jul 13, 2010

Filed:

Oct 24, 2006

Appl. No.:

11/552350

Inventors:

Dane T. Mrazek - Redwood City CA, US
Sameer M. Gauria - Mountain View CA, US
James C. Bowman - Pescadero CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 15/00

US Classification:

345501

Abstract:

Disclosed are an apparatus, a method, a programmable graphics processing unit (“GPU”), a computer device, and a computer medium to facilitate, among other things, the generation of parallel data streams to effect parallel processing in at least a portion of a graphics pipeline of a GPU. In one embodiment, an input of the apparatus receives graphics elements in a data stream of graphics elements. The graphics pipeline can use the graphics elements to form computer-generated images. The apparatus also can include a transposer configured to produce parallel attribute streams. Each of the parallel attribute streams includes a type of attribute common to the graphics elements. In one embodiment, the transposer can be configured to convert at least a portion of the graphics pipeline from a single data stream to multiple data streams (e. g. , executable by multiple threads of execution) while reducing the memory size requirements to implement such a conversion.

US Patent:

7796137, Sep 14, 2010

Filed:

Oct 24, 2006

Appl. No.:

11/552415

Inventors:

Dane T. Mrazek - Redwood City CA, US
Sameer M. Gauria - Mountain View CA, US
James C. Bowman - Pescadero CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G09G 5/36
G06F 12/08

US Classification:

345557, 711 3

Abstract:

Disclosed are an apparatus, a system, a method, a graphics processing unit (“GPU”), a computer device, and a computer medium to implement a pool of independent enhanced tags to, among other things, decouple a dependency between tags and cachelines. In one embodiment, an enhanced tag-based cache structure includes a tag repository configured to maintain a pool of enhanced tags. Each enhanced tag can have a match portion configured to form an association between the enhanced tag and an incoming address. Also, an enhanced tag can have a data locator portion configured to locate a cacheline in the cache in response to the formation of the association. The data locator portion enables the enhanced tag to locate multiple cachelines. Advantageously, the enhanced tag-based cache structure can be formed to adjust the degree of reusability of the enhanced tags independent from the degree of latency tolerance for the cacheline repository.

US Patent:

7797258, Sep 14, 2010

Filed:

Nov 2, 2006

Appl. No.:

11/556141

Inventors:

James C. Bowman - Pescadero CA, US
Dane T. Mrazek - Redwood City CA, US
Sameer M. Gauria - Mountain View CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06E 1/00
G06E 3/00
G06F 15/18
G06G 7/00
G06T 1/00
G06T 15/00

US Classification:

706 19, 345522

Abstract:

A graphics system includes a transposer. A read scheduler utilizes a minimum cost analysis to schedule a read transfer order for the transposer to minimize the total number of passes required to process a set of input vectors.

US Patent:

8237725, Aug 7, 2012

Filed:

Nov 5, 2007

Appl. No.:

11/935239

Inventors:

James C. Bowman - Pescadero CA, US
Dane T. Mrazek - Redwood City CA, US
Sameer M. Gauria - Santa Clara CA, US

Assignee:

NVIDA Corporation - Santa Clara CA

International Classification:

G09G 5/36

US Classification:

345557, 345502, 345530

Abstract:

A vertex cache within a graphics processor is configured to operate as a conventional round-robin streaming cache when per-vertex state changes are not used and is configured to operate as a random access storage buffer when per-vertex state changes are used. Batches of vertices that define primitives and state changes are output to parallel processing units for processing according to vertex shader program. In addition to allowing per-vertex state changes, the vertex cache is configured to store vertices for primitive topologies that use anchor points, such as triangle strips, line loops, and polygons.

US Patent:

8542247, Sep 24, 2013

Filed:

Jul 17, 2009

Appl. No.:

12/505398

Inventors:

Ziyad S. Hakura - Mountain View CA, US
John Erik Lindholm - Saratoga CA, US
Emmett M. Kilgariff - San Jose CA, US
Robert Ohannessian - Austin TX, US
Scott R. Whitman - Saratoga CA, US
James C. Bowman - Pescadero CA, US
Patrick R. Brown - Raleigh NC, US
Ross A. Cunniff - Fort Collins CO, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G09G 5/00

US Classification:

345620

Abstract:

One embodiment of the invention sets forth a mechanism for compiling a vertex shader program into two portions, a culling portion and a shading portion. The culling portion of the compiled vertex shader program specifies vertex attributes and instructions of the vertex shader program needed to determine whether early vertex culling operations should be performed on a batch of vertices associated with one or more primitives of a graphics scene. The shading portion of the compiled vertex shader program specifies the remaining vertex attributes and instructions of the vertex shader program for performing vertex lighting and performing other operations on the vertices in the batch of vertices. When the compiled vertex shader program is executed by graphics processing hardware, the shading portion of the compiled vertex shader is executed only when early vertex culling operations are not performed on the batch of vertices.

US Patent:

8558842, Oct 15, 2013

Filed:

Mar 12, 2010

Appl. No.:

12/723266

Inventors:

Philip B. Johnson - Campbell CA, US
James C. Bowman - Pescadero CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G09G 5/00
G06F 15/16

US Classification:

345581, 345502

Abstract:

One embodiment of the present invention sets forth a technique for detecting duplicate vertex indices in parallel and batching indices defining multiple primitives for parallel primitive processing. A lookback cache breaks the dependent loop for the miss processing. Because each index is compared to all previous indices (duplicate or not), each index is not dependent on whether the previous indices have hit or missed. This allows the comparison operation that detects the duplicate vertex indices to be fully pipelined. The duplicate vertex indices are removed to reduce the number of indices that define the primitives in the batch. Multiple, independent rasterizer units operate concurrently on the different batches of graphics primitives to render multiple primitives per system clock.

US Patent:

8564616, Oct 22, 2013

Filed:

Jul 17, 2009

Appl. No.:

12/505402

Inventors:

Ziyad S. Hakura - Gilory CA, US
John Erik Lindholm - Saratoga CA, US
Emmett M. Kilgariff - San Jose CA, US
Robert Ohannessian - Austin TX, US
Scott R. Whitman - Saratoga CA, US
James C. Bowman - Pescadero CA, US
Patrick R. Brown - Raleigh NC, US
Ross A. Cunniff - Fort Collins CO, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G09G 5/00

US Classification:

345620

Abstract:

One embodiment of the invention sets forth a mechanism for compiling a vertex shader program into two portions, a culling portion and a shading portion. The culling portion of the compiled vertex shader program specifies vertex attributes and instructions of the vertex shader program needed to determine whether early vertex culling operations should be performed on a batch of vertices associated with one or more primitives of a graphics scene. The shading portion of the compiled vertex shader program specifies the remaining vertex attributes and instructions of the vertex shader program for performing vertex lighting and performing other operations on the vertices in the batch of vertices. When the compiled vertex shader program is executed by graphics processing hardware, the shading portion of the compiled vertex shader is executed only when early vertex culling operations are not performed on the batch of vertices.