James C Culp

US Patent:

20040210863, Oct 21, 2004

Filed:

Apr 16, 2003

Appl. No.:

10/249524

Inventors:

James Culp - Downingtown PA, US
Mark Lavin - Katonah NY, US
Robert Sayah - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F017/50

US Classification:

716/021000, 716/004000

Abstract:

A method of predicting overlay failure of circuit configurations on adjacent, lithographically produced layers of a semiconductor wafer comprises providing design configurations for circuit portions to be lithographically produced on one or more adjacent layers of a semiconductor wafer, and then predicting shape and alignment for each circuit portions on each adjacent layer using one or more predetermined values for process fluctuation or misalignment error. The method then determines dimension of overlap of the predicted shape and alignment of the circuit portions, and compares the determined dimension of overlap to a theoretical minimum to determine whether the predicted dimension of overlap fails. Using different process fluctuation values and misalignment error values, the steps are then iteratively repeated on the provided design configurations to determine whether the predicted dimension of overlap fails, and a report is made of the measure of failures.

US Patent:

54997852, Mar 19, 1996

Filed:

Sep 15, 1994

Appl. No.:

8/306745

Inventors:

James P. Roberts - Claymont DE
James D. Culp - Newark DE
David G. Miller - Philadelphia PA
Martin R. Sarsfield - Wilmington DE

Assignee:

The Boeing Company - Seattle WA

International Classification:

B64D 112

US Classification:

2441374

Abstract:

A method and apparatus for automatically jettisoning cargo carried by a dual-point suspension system when a suspension system failure is detected. Three conditions must be satisfied before a load is jettisoned. The average value of the load and an instantaneous value of the load on a hook must have fallen below a threshold value (zero load condition). A threshold amount of the load must have shifted from one hook to the other (dynamic load split condition). A threshold amount of an initial hook load must have been lost within a short period of time (rapid rate-of-decrease condition). For all three conditions, the threshold amount or value is adaptively set based on the actual load carried by the dual-point suspension. If all three conditions are satisfied for either the forward or the aft hook, the cargo is jettisoned. Additionally, a fourth condition that detects whether a structural limit of a hook has been exceeded is evaluated.

US Patent:

20150255342, Sep 10, 2015

Filed:

May 26, 2015

Appl. No.:

14/721323

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton On Hudson NY, US
Andrew H. Simon - Fishkill NY, US

International Classification:

H01L 21/768

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

US Patent:

20150255343, Sep 10, 2015

Filed:

May 26, 2015

Appl. No.:

14/721361

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton On Hudson NY, US
Andrew H. Simon - Fishkill NY, US

International Classification:

H01L 21/768

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

US Patent:

20150255398, Sep 10, 2015

Filed:

May 26, 2015

Appl. No.:

14/721410

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton On Hudson NY, US
Andrew H. Simon - Fishkill NY, US

International Classification:

H01L 23/532

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

US Patent:

20140203435, Jul 24, 2014

Filed:

Jan 18, 2013

Appl. No.:

13/744705

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton on Hudson NY, US
Andrew H. Simon - Fishkill NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/768
H01L 23/532

US Classification:

257751, 438643

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.