James Steven Divine

US Patent:

6385704, May 7, 2002

Filed:

Nov 14, 1997

Appl. No.:

08/969884

Inventors:

Raghunath Rao - Austin TX
Miroslav Dokic - Austin TX
Zheng Luo - Austin TX
Jeffrey Niehaus - Austin TX
James Divine - Austin TX

Assignee:

Cirrus Logic, Inc.

International Classification:

G06F 1200

US Classification:

711151, 711152

Abstract:

A method of operating shared memory in a multiple processor system. A token is by default maintained with a first processor, the token enabling access to shared memory. A determination is made that a second processor requires access to shared memory. A determination is also made as to whether the first processor is accessing to the shared memory. The token is transferred the second processor if the first processor is not accessing the shared memory. The second processor accesses the shared memory with the token.

US Patent:

61015989, Aug 8, 2000

Filed:

Nov 14, 1997

Appl. No.:

8/970372

Inventors:

Miroslav Dokic - Austin TX
Raghunath Rao - Austin TX
Zheng Luo - Austin TX
Jeffrey Niehaus - Austin TX
James Divine - Austin TX

Assignee:

Cirrus Logic, Inc.

International Classification:

G06F 0944

US Classification:

712227

Abstract:

A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.

US Patent:

60817836, Jun 27, 2000

Filed:

Nov 14, 1997

Appl. No.:

8/970979

Inventors:

James Divine - Austin TX
Jeffrey Niehaus - Austin TX
Miroslav Dokic - Austin TX
Raghunath Rao - Austin TX
Terry Ritchie - Austin TX
Baker Scott - Boulder CO
John Pacourek - Austin TX
Zheng Luo - Austin TX

Assignee:

Cirrus Logic, Inc.

International Classification:

G10L 2100

US Classification:

704500

Abstract:

An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.

US Patent:

61450073, Nov 7, 2000

Filed:

Nov 14, 1997

Appl. No.:

8/969883

Inventors:

Miroslav Dokic - Austin TX
Raghunath Rao - Austin TX
Jeffrey Niehaus - Austin TX
Zheng Luo - Austin TX
James Divine - Austin TX

Assignee:

Cirrus Logic, Inc.

International Classification:

G06F 1300

US Classification:

709230

Abstract:

A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a message is written into a second register with the first processor. The pending flag is set to a second selected logic state with the first processor and an interrupt to the second processor is generated. The message is read from the second register with the second processor when the pending flag is in the second logic state. The pending flag set to the first logic state with the second processor.

US Patent:

58482890, Dec 8, 1998

Filed:

Nov 27, 1992

Appl. No.:

7/982327

Inventors:

Charles F. Studor - Austin TX
James S. Divine - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 930

US Classification:

39580032

Abstract:

An extensible central processing unit (CPU) (12 or 12'). By modifying the architecture of a new or prior art CPU, a new or prior art CPU can be made extensible so that new instructions can be added in a simple and cost effective manner to meet differing customer needs. The term "extensible" in regard to a CPU is used to mean that new instructions can be added to the CPU simply by adding certain designated circuitry, without the need to significantly change the existing CPU circuitry. In some embodiments, the additional designated circuitry may include control circuitry in the form of CPU control extension circuitry (52 or 152). In some embodiments, the additional circuitry may include non-control circuitry in the form of execution unit extension circuitry (153).

US Patent:

54107210, Apr 25, 1995

Filed:

Dec 24, 1992

Appl. No.:

7/996749

Inventors:

James S. Divine - Austin TX
Charles F. Studor - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 700

US Classification:

395800

Abstract:

A data processor (10) increments a sixteen bit program counter value using an arithmetic logic unit, ALU, (224) and an eight bit incrementer(250). The ALU increments a low byte of the program counter value. A carry generated by incrementing the low byte is propagated to the incrementer. The incrementer then increments the high byte of the program counter value. Subsequently, the high and low bytes of the program counter value are respectively stored in a high and low program counter register (200, 206). Therefore, eight bits of an incrementer which would have typically been required to implement an incrementer for the low byte of the program counter value have been eliminated without a reduction in functionality of the data processor.

US Patent:

56806329, Oct 21, 1997

Filed:

Dec 24, 1992

Appl. No.:

7/996744

Inventors:

Charles F. Studor - Austin TX
James S. Divine - Austin TX
Michael I. Catherwood - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 500

US Classification:

395800

Abstract:

A data processing system providing an extensible register and method thereof. A new CPU has an extensible index register. The new CPU is object code compatible with the old CPU having an 8-bit index register, yet the index register of the new CPU can be effectively extended to 16 bits when new instructions are used. As a consequence, the user is able to make the choice between using assembly code software written for the old CPU and having the functionality of an 8-bit index register, or writing new assembly code software for the new CPU and having the functionality of a 16-bit index register.

US Patent:

62532936, Jun 26, 2001

Filed:

Jan 14, 2000

Appl. No.:

9/483290

Inventors:

Raghunath Rao - Austin TX
Miroslav Dokic - Austin TX
Zheng Luo - Austin TX
Jeffrey Niehaus - Austin TX
James Divine - Austin TX

Assignee:

Cirrus Logic, Inc.

International Classification:

G06F 1200
G06F 1700
G06F 15167
G10L 2100

US Classification:

711147

Abstract:

A method of processing a stream of audio information received by a multiple processor audio decoder. Processing operations are performed by a first processor on the stream of audio information to produce at set of results. The first processor writes the set of results into a shared memory and a flag is set indicating that the results are ready. In response to the flag, a second processor reads the results from shared memory. When the results have been read from shared memory, the second processor sends a command to the first processor. The first processor then clears the flag.