James D Doyle

US Patent:

6629254, Sep 30, 2003

Filed:

Jun 29, 2000

Appl. No.:

09/607565

Inventors:

Syed R. Naqvi - Tempe AZ
James T. Doyle - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 112

US Classification:

713401, 713400, 713500, 713600, 327 2, 327141, 327158

Abstract:

An apparatus includes a memory buffer, a first signal buffer, a locked loop circuit and a feedback circuit. The memory buffer provides a data signal to an output terminal of the memory buffer in response to a first clock signal. The first signal buffer is coupled between the output terminal of the memory buffer and a data line of a bus. The first signal buffer introduces a first delay. The locked loop circuit furnishes the first clock signal to establish a predefined relationship between a phase of a second clock signal and a phase of a third clock signal. The feedback circuit produces the second clock signal in response to the first clock signal. The feedback circuit includes a second signal buffer to introduce a second delay to the second clock, and the second delay is approximately the same as the first delay that is introduced by the first signal buffer.

US Patent:

48354872, May 30, 1989

Filed:

Apr 14, 1988

Appl. No.:

7/181607

Inventors:

James T. Doyle - Phoenix AZ
Bart R. McDaniel - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 316
G05F 156

US Classification:

330277

Abstract:

A voltage to current converter circuit manufactured with a MOS process generates a linear reference current over a wide bandwidth and operates with an input signal that varies to either supply rail. A voltage divider network scales an input voltage for conversion to a linear current by a cascode current mirror and a gain resistor. The value of the gain resistor determines the transconductance of the conversion from voltage to current. A second current mirror provides feedback to keep the reference current accurate. An output stage makes available high impedance source and sink current output terminals wherein a source current and a sink current relative to the reference current are provided. Several voltage to current converter circuits may be coupled together to provide a addition, subtraction, multiplication, and other circuit and system functions.

US Patent:

48454443, Jul 4, 1989

Filed:

Mar 7, 1988

Appl. No.:

7/164686

Inventors:

James T. Doyle - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03B 536
H03B 2500

US Classification:

331116FE

Abstract:

A crystal oscillator comprising a crsytal and an inverter amplifier which utilizes a current mirror to provide a voltage output having a frequency double the frequency of the voltage waveform present in the inverter amplifier.

US Patent:

63236745, Nov 27, 2001

Filed:

Feb 29, 2000

Appl. No.:

9/515270

Inventors:

Udbhava A. Shrivastava - Tempe AZ
James T. Doyle - Chandler AZ
Edward J. Bawolek - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19003

US Classification:

326 30

Abstract:

A system includes a transmission line, a driver, a load, a compensation capacitor and a compensation resistor. An output terminal of the driver is coupled to one end of the transmission line, and the load is coupled to the other end of the transmission line. The compensation capacitor is coupled in parallel with the output terminal of the driver, and the compensation resistor is coupled in series between the other end of the transmission line and the load.

US Patent:

20220231607, Jul 21, 2022

Filed:

Jan 14, 2022

Appl. No.:

17/575842

Inventors:

- London, GB
James T. Doyle - Phoenix AZ, US
Ambreesh Bhattad - Swindon, GB

International Classification:

H02M 3/158
H02M 1/00

Abstract:

The present document relates to power converters. A power converter may be configured to convert an input voltage at an input of the power converter into an output voltage at an output of the power converter. The power converter may comprise a first switching circuit with a first inductor, a first high-side switching element, and a first low-side switching element. The power converter may comprise a second switching circuit with a second inductor, a second high-side switching element, and a second low-side switching element. The power converter may comprise a capacitive element having a first terminal coupled to the first high-side switching element and to the second high-side switching element and having a second terminal coupled to the first low-side switching element at a first node. The power converter may comprise a third switching element coupled between the first node and the output of the power converter.