James L Duda

US Patent:

6907508, Jun 14, 2005

Filed:

Feb 26, 2003

Appl. No.:

10/376354

Inventors:

Glenn Dearth - Groton MA, US
Carl J. Lindeborg - Shrewsbury MA, US
Robin L. Brown - Leominster MA, US
James A. Duda - Waltham MA, US
Sudhir Srinivasan - Chelmsford MA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F012/00

US Classification:

711173, 711 5, 711119, 711122, 711129, 711147, 711153, 711170, 713 1, 713100

Abstract:

In a digital data processing system having a memory component, a structure and method for managing available memory resources. Free pointers to respective free memory blocks are stored in memory blocks maintained as a linked list. In a system having a hierarchically-organized memory component, a small number of the free pointers are maintained at a relatively higher performance level of the memory and the balance of the free pointers are maintained at a relatively lower performance level of the memory.

US Patent:

8621194, Dec 31, 2013

Filed:

Aug 31, 2010

Appl. No.:

12/872733

Inventors:

James A. Duda - Waltham MA, US
Andre M. Hassan - Windham NH, US
Nathan J. Dohm - Natick MA, US
Robert Swope Fleming - Arlington MA, US
Michael Joseph Schaffstein - Waltham MA, US

Assignee:

Conexant Systems, Inc. - Irvine CA

International Classification:

G06F 15/177

US Classification:

713 2, 711103, 714 611

Abstract:

A system for booting a processor from NAND flash, comprising a NAND agnostic boot controller and a NAND flash device, wherein the NAND flash device further comprises a boot wrapper storing boot code in a predetermined format.

US Patent:

62758772, Aug 14, 2001

Filed:

Oct 27, 1998

Appl. No.:

9/179946

Inventors:

James Duda - Waltham MA

International Classification:

G06F 1314

US Classification:

710 23

Abstract:

A direct memory access controller is provided which utilizes a single dedicated controller to control all or substantially all memory accesses in a computer system, both memory-to-memory accesses within the system and transfers between system memory and various system peripherals. At least portions of the controller are time shared by various channels, each channel performing data transfers in a selected direction between a system memory component and a second component which may be a peripheral, another memory component or the like. An arbiter is provided as part of the controller for determining the channel using shared resources at any given time. Where one of the peripherals is a variable length packetized data source, multiple subchannels may be provided for transfers of data for such source into system memory, each such subehannel being for transfers to buffers of different size. Efficient memory utilization is achieved by determining the size of an incoming variable length packet and having the transfer performed through the channel servicing the smallest available buffer in which incoming variable length packetized data will fit.