James Joseph Eldredge

US Patent:

6557059, Apr 29, 2003

Filed:

Oct 12, 1999

Appl. No.:

09/416599

Inventors:

James R. Nottingham - Boise ID
Calvin K. McDonald - Boise ID
James G. Eldredge - Meridian ID

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 1300

US Classification:

710 62, 710 4, 710 5, 710 7, 710 8, 710 20, 710 31, 710107, 710110, 710268

Abstract:

The invention provides apparatus for the transfer of data/command between a master controller and one or more client controllers. The apparatus in accordance with the invention includes a bi-directional data bus for conveying plural bits of data or command between a master controller and one or more client controllers; direction signal controlling the direction in which data or command bits are conveyed on the data bus as between the master controller and a connected one of the one or more client controllers; a pair of ready signals including a transmit ready signal asserted by a source of data or command bits placed on the data bus and including a receive ready signal asserted by a destination for the data or command bits placed on the data bus; and a clock signal for indicating the presence of valid data or command bits on the data bus on a leading or trailing edge thereof. Preferably, a command/data signal is also provided to indicate the type of information placed on the data bus by the source. In accordance with one aspect of the invention, the pair of ready signals includes a bi-directional transmit ready signal and a bi-directional receive ready signal corresponding to each one of the one or more client controllers, and wherein the functions of the transmit ready signals and the receive ready signals within the interface are modified by the state of the direction signal, whereby under a first state of the direction signal a transmit ready signal is asserted by the master controller to select one of the one or more client controllers as a destination for the data or command bits placed on the data bus and a corresponding receive ready signal is asserted by the one client controller to indicate that the one client controller is ready to receive the data or command bits placed on the data bus and whereby under a second state of the direction signal a transmit ready signal is asserted by the one or more client controllers to indicate the one or more client controllers is ready to transmit data or command bits placed on the data bus and a corresponding receive ready signal is asserted by the master controller to acknowledge receipt of data or command bits placed on the data bus by the one client controller.

US Patent:

6753988, Jun 22, 2004

Filed:

Mar 29, 2002

Appl. No.:

10/112383

Inventors:

James G. Eldredge - Meridian ID

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H04N 146

US Classification:

358535, 358518, 358523, 358525

Abstract:

A color data converter includes a plurality of memories configured to store lattice points for a color space. The lattice points of the first axis are assigned to memories in a sequential manner. The lattice points along the other two axes are assigned to memories in an alternating manner.

US Patent:

6792499, Sep 14, 2004

Filed:

Feb 1, 2002

Appl. No.:

10/061914

Inventors:

James G. Eldredge - Meridian ID

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 1200

US Classification:

711 5, 711202

Abstract:

A microprocessor system is provided that includes a first memory bank having a first base address and a second memory bank having a second base address. A memory controller is adapted to register the first and second base addresses. A swap command is adapted to instruct the memory controller to swap the first and second base addresses. A microprocessor issues the swap command. The memory controller includes a first base address register adapted to register the first base address and a second base address register adapted to register the second base address. A command register is adapted to register the swap command. In one embodiment, the first memory bank is a DRAM bank and the second memory bank is a ROM bank. The swap command instructs the memory controller to swap the first and second base addresses before temporary storage is established in the DRAM bank.

US Patent:

6801212, Oct 5, 2004

Filed:

Mar 29, 2002

Appl. No.:

10/112013

Inventors:

James G. Eldredge - Meridian ID

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G09G 502

US Classification:

345589, 345606

Abstract:

An interpolation scheme uses cubic subdivision to index a position of an input color value in a color space relative to neighboring vertices. The indexed position of the input color value is expanded and the neighboring vertices are combined together according to the expanded index to generate an output color value.

US Patent:

6996655, Feb 7, 2006

Filed:

Dec 21, 2001

Appl. No.:

10/028029

Inventors:

R. Samuel Lee - Meridian ID, US
James G. Eldredge - Meridian ID, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 13/00
G06F 12/00

US Classification:

710308, 710 22

Abstract:

Peer-to-peer Direct Memory Access (DMA) permits the efficient transfer of data from one DMA capable Application Specific Integrated Circuit (ASIC) block to another without accessing memory. The peer-to-peer transfer can be done over a standard AMBA AHB bus architecture without side band signals and without violating the AHB specification.

US Patent:

7466042, Dec 16, 2008

Filed:

Apr 6, 2005

Appl. No.:

11/101036

Inventors:

James G. Eldredge - Meridian ID, US

Assignee:

Flexsil, Inc. - Meridian ID

International Classification:

G01R 1/20
H02J 7/00

US Classification:

307154, 320106

Abstract:

A power converter capable of providing a range of DC voltages to an external device and a method of providing a range of DC power are provided. The power converter comprises a supply circuit for receiving a request for DC power and for providing the requested DC power. The supply circuit comprises a detection circuit for sensing a connection to an external device, a source controller circuit for determining a DC output power required by the external device, and a converter circuit for generating the required DC output power. The external device comprises a device controller circuit for communicating the request for DC power. A first conductor provides a path for the device to communicate the required DC power to the power converter and for the power converter to supply the required DC power. A second conductor provides a common reference for conducting return current to the power converter.

US Patent:

20070029879, Feb 8, 2007

Filed:

Aug 4, 2005

Appl. No.:

11/198750

Inventors:

James Eldredge - Meridian ID, US

International Classification:

H02J 1/10

US Classification:

307018000

Abstract:

Two embodiments for distributing DC power in a building are provided. In the first embodiment, a centralized DC power converter is connected to the building's standard AC power wiring. The centralized DC power converter generates DC power for at least one DC-powered electronic device. The DC power is routed to DC outlets throughout the building over DC conductor sets. A second embodiment embeds a DC power converter in the outlet, which connects to standard AC power wiring. The embedded DC power converter then generates DC power for at least one DC-powered electronic device. A DC power outlet is also provided which may comprise one or more DC power receptacles or DC power cords and plugs, one or more status indicator LEDs, a retraction mechanism for each of the DC power cords, a cooling fan, and an embedded DC power converter. The DC power converters may be universal DC power converters.

US Patent:

20070228831, Oct 4, 2007

Filed:

Jun 6, 2007

Appl. No.:

11/759123

Inventors:

James Eldredge - Meridian ID, US

Assignee:

Flexsil, Inc. - Eagle ID

International Classification:

H02J 1/00

US Classification:

307029000

Abstract:

A power converter capable of providing a range of DC voltages to an external device and a method of providing a range of DC power are provided. The power converter comprises a supply circuit for receiving a request for DC power and for providing the requested DC power. The supply circuit comprises a detection circuit for sensing a connection to an external device, a source controller circuit for determining a DC output power required by the external device, and a converter circuit for generating the required DC output power. The external device comprises a device controller circuit for communicating the request for DC power. A first conductor provides a path for the device to communicate the required DC power to the power converter and for the power converter to supply the required DC power. A second conductor provides a common reference for conducting return current to the power converter.