James H Ermer

US Patent:

6380601, Apr 30, 2002

Filed:

Mar 29, 1999

Appl. No.:

09/280771

Inventors:

James H. Ermer - Burbank CA
Li Cai - Northridge CA
Moran Haddad - Winnetka CA
Bruce T. Cavicchi - North Hollywood CA
Nasser H. Karam - Northridge CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

H01L 31042

US Classification:

257440, 257184, 136249, 136261, 438 77, 438 94

Abstract:

A multilayer semiconductor structure includes a germanium substrate having a first surface. The germanium substrate has two regions, a bulk p-type germanium region, and a phosphorus-doped n-type germanium region adjacent to the first surface. A layer of a phosphide material overlies and contacts the first surface of the germanium substrate. A layer of gallium arsenide overlies and contacts the layer of the phosphide material, and electrical contacts may be added to form a solar cell. Additional photovoltaic junctions may be added to form multijunction solar cells. The solar cells may be assembled together to form solar panels.

US Patent:

6586669, Jul 1, 2003

Filed:

Jun 6, 2001

Appl. No.:

09/876193

Inventors:

Richard Roland King - Newbury Park CA
James H. Ermer - Burbank CA
Peter Colter - Canyon County CA
Nasser H. Karam - Northridge CA

Assignee:

The Boeing Company - Seattle WA

International Classification:

H01L 3104

US Classification:

136249, 136255, 136252, 136261, 136262, 257431, 257461

Abstract:

A perfectly or approximately lattice-matched semiconductor layer for use in an electronic or optoelectronic device. Perfectly lattice-matched (âPLMâ) semiconductor layers prevent or lessen the formation and propagation of crystal defects in semiconductor devices, defects that can decrease the performance characteristics of the device. For some semiconductors, the ability to optimize composition-dependent properties over the wider range of compositions that approximately lattice-matched (âALMâ) semiconductor layers allows is more advantageous than the lower strain and dislocation density encountered for PLM layers. In addition, PLM cell layers and ALM cell layers are also expected to result in improved radiation resistance characteristics for some semiconductor devices.

US Patent:

7119271, Oct 10, 2006

Filed:

Jan 31, 2003

Appl. No.:

10/356028

Inventors:

Richard Roland King - Thousand Oaks CA, US
Peter C. Colter - Canyon Country CA, US
James H. Ermer - Burbank CA, US
Moran Haddad - Winnetka CA, US
Nasser H. Karam - Northridge CA, US

Assignee:

The Boeing Company - Chicago IL

International Classification:

H01L 31/04
H01L 21/02

US Classification:

136252, 136261, 136262, 438 57

Abstract:

A photovoltaic cell or other optoelectronic device having a wide-bandgap semiconductor used in the window layer. This wider bandgap is achieved by using a semiconductor composition that is not lattice-matched to the cell layer directly beneath it and/or to the growth substrate. The wider bandgap of the window layer increases the transmission of short wavelength light into the emitter and base layers of the photovoltaic cell. This in turn increases the current generation in the photovoltaic cell. Additionally, the wider bandgap of the lattice mismatched window layer inhibits minority carrier injection and recombination in the window layer.

US Patent:

7122734, Oct 17, 2006

Filed:

Oct 23, 2002

Appl. No.:

10/281302

Inventors:

Christopher M. Fetzer - Saugus CA, US
James H. Ermer - Burbank CA, US
Richard R. King - Thousand Oaks CA, US
Peter C. Cotler - Canyon Country CA, US

Assignee:

The Boeing Company - Chicago IL

International Classification:

H01L 31/04
H01L 31/18

US Classification:

136252, 136262, 257 18, 257103, 257431, 257463, 257615, 257629, 257635, 438 93, 438796, 438797

Abstract:

A method of reducing propagation of threading dislocations into active areas of an optoelectronic device having a III–V material system includes growing a metamorphic buffer region in the presence of an isoelectronic surfactant. A first buffer layer may be lattice matched to an adjacent substrate and a second buffer layer may be lattice matched to device layers disposed upon the second buffer layer. Moreover, multiple metamorphic buffer layers fabricated in this manner may be used in a single given device allowing multiple layers to have their band gaps and lattice constants independently selected from those of the rest of the device.

US Patent:

7126052, Oct 24, 2006

Filed:

Oct 2, 2002

Appl. No.:

10/263626

Inventors:

Christopher M. Fetzer - Valencia CA, US
James H. Ermer - Burbank CA, US
Richard R. King - Thousand Oaks CA, US
Peter C. Cotler - Canyon Country CA, US

Assignee:

The Boeing Company - Chicago IL

International Classification:

H01L 31/0264
H01L 31/04

US Classification:

136252, 136256, 136262, 136244, 136255, 136249, 257102, 257103, 257 79, 257228, 257431, 257463, 257609

Abstract:

A method of disordering a layer of an optoelectronic device including; growing a plurality of lower layers; introducing an isoelectronic surfactant; growing a layer; allowing the surfactant to desorb; and growing subsequent layers all performed at a low pressure of 25 torr.

US Patent:

7202542, Apr 10, 2007

Filed:

Dec 17, 2003

Appl. No.:

10/739755

Inventors:

Hojun Yoon - Stevenson Ranch CA, US
Richard King - Thousand Oaks CA, US
Jerry R. Kukulka - Santa Clarita CA, US
James H. Ermer - Burbank CA, US
Maggy L. Lau - Hacienda Heights CA, US

Assignee:

The Boeing Company - Chicago IL

International Classification:

H01L 27/14

US Classification:

257428, 257434, 257751

Abstract:

A semiconductor structure includes a semiconductor substrate, a semiconductor active region, a semiconductor contact layer, at least one metal migration semiconductor barrier layer, and a metal contact. The metal migration semiconductor barrier layer may be embedded within the semiconductor contact layer. Furthermore, the metal migration semiconductor barrier layer may be located underneath or above and in intimate contact with the semiconductor contact layer. The metal migration semiconductor barrier layer and the semiconductor contact layer form a contact structure that prevents metals from migrating from the metal contact into the semiconductor active layer during long-term exposure to high temperatures. By providing a robust contact structure that may be used in semiconductor structures, for example in solar cells that power spacecraft or terrestrial solar cells used under concentrated sunlight, the high temperature reliability of the semiconductor structure will be improved and the operation time will be prolonged.

US Patent:

7626116, Dec 1, 2009

Filed:

Feb 23, 2006

Appl. No.:

11/361976

Inventors:

Christopher M. Fetzer - Santa Clarita CA, US
James H. Ermer - Burbank CA, US
Richard R. King - Thousand Oaks CA, US
Peter C. Cotler - Canyon Country CA, US

Assignee:

The Boeing Company - Chicago IL

International Classification:

H01L 31/00

US Classification:

136255, 136256, 136262

Abstract:

A method of reducing propagation of threading dislocations into active areas of an optoelectronic device having a III-V material system includes growing a metamorphic buffer region in the presence of an isoelectronic surfactant. A first buffer layer may be lattice matched to an adjacent substrate and a second buffer layer may be lattice matched to device layers disposed upon the second buffer layer. Moreover, multiple metamorphic buffer layers fabricated in this manner may be used in a single given device allowing multiple layers to have their band gaps and lattice constants independently selected from those of the rest of the device.

US Patent:

7687386, Mar 30, 2010

Filed:

Feb 20, 2007

Appl. No.:

11/676953

Inventors:

Hojun Yoon - Stevenson Ranch CA, US
Richard King - Thousand Oaks CA, US
Jerry R. Kukulka - Santa Clarita CA, US
James H. Ermer - Burbank CA, US
Maggy L. Lau - Hacienda Heghts CA, US

Assignee:

The Boeing Company - Chicago IL

International Classification:

H01L 21/28

US Classification:

438572, 257E21386, 257E21387

Abstract:

A semiconductor structure includes a semiconductor substrate, a semiconductor active region, a semiconductor contact layer, at least one metal migration semiconductor barrier layer, and a metal contact. The metal migration semiconductor barrier layer may be embedded within the semiconductor contact layer. Furthermore, the metal migration semiconductor barrier layer may be located underneath or above and in intimate contact with the semiconductor contact layer. The metal migration semiconductor barrier layer and the semiconductor contact layer form a contact structure that prevents metals from migrating from the metal contact into the semiconductor active layer during long-term exposure to high temperatures. By providing a robust contact structure that may be used in semiconductor structures, for example in solar cells that power spacecraft or terrestrial solar cells used under concentrated sunlight, the high temperature reliability of the semiconductor structure will be improved and the operation time will be prolonged.