James L Farrell

US Patent:

6473888, Oct 29, 2002

Filed:

Dec 10, 1998

Appl. No.:

09/208780

Inventors:

Nevine Nassif - Arlington MA
Madhav Desai - Mumbai, IN
James Arthur Farrell - Harvard MA
Roy Badeau - Berlin MA
Nicholas Lee Rethman - North Andover MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1750

US Classification:

716 6, 716 5, 716 4

Abstract:

The present invention relates to a method and apparatus for determining capacitance and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

US Patent:

6542987, Apr 1, 2003

Filed:

Dec 17, 1999

Appl. No.:

09/465689

Inventors:

Timothy Charles Fischer - Maynard MA
Daniel Lawrence Leibholz - Cambridge MA
James Arthur Farrell - Harvard MA

Assignee:

Hewlett-Packard Development Company L.P. - Houston TX

International Classification:

G06F 930

US Classification:

712217, 712219, 712245, 714 21

Abstract:

In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K-2, the number of instructions issued for cycle K-1 and the number of instructions speculatively issued in cycle K-1 that have produced a cache hit, and subtracting from the sum the number of instructions enqueued for cycle K-1. The result indicates the number of invalid instructions in the queue cycle K. The number of invalid entries instructions, the number of issued instructions, and the number of enqueued instructions are preferably represented as flat vectors, so that adding is performed by shifting in one direction, while subtracting is performed by shifting in the opposite direction. The result is compared with either the number of instructions to be enqueued in the present cycle, which number is encoded, or with a predetermined value. A stall signal is generated if the indicative value is less than the encoded number or the predetermined value.

US Patent:

6658506, Dec 2, 2003

Filed:

Apr 14, 1999

Appl. No.:

09/292051

Inventors:

Nevine Nassif - Arlington MA
James Arthur Farrell - Harvard MA
Dale Hayward Hall - Northborough MA
Gill Watt - Acton MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 104

US Classification:

710 58, 713500, 455114, 375296

Abstract:

A system for accurately determining Elmore delays in DCVSL structures is disclosed. The system uses circuit simulation to determine models for Elmore delays through devices within specific circuit structures. The circuit structures include DCVSL circuits to accurately model performance of devices with such a structure. The system also determines discharge characteristics for DCVSL circuits using simulation. In order to determine Elmore delays, the system analyzes a circuit representation to locate DCVSL structures. The discharge characteristics and models are used to determine Elmore delays for each structure located.

US Patent:

6877142, Apr 5, 2005

Filed:

Aug 13, 2002

Appl. No.:

10/218079

Inventors:

Nevine Nassif - Arlington MA, US
Madhav Desai - Mumbai, IN
James Arthur Farrell - Harvard MA, US
Roy Badeau - Berlin MA, US
Nicholas Lee Rethman - North Andover MA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F017/50

US Classification:

716 6, 716 4, 716 5

Abstract:

The present invention relates to a method and apparatus for determining capacitances and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

US Patent:

8090930, Jan 3, 2012

Filed:

Jan 31, 2003

Appl. No.:

10/356943

Inventors:

Timothy Charles Fischer - Maynard MA, US
Daniel Lawrence Leibholz - Cambridge MA, US
James Arthur Farrell - Harvard MA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 9/315
G06F 13/40
G06F 13/20

US Classification:

712215, 711144, 710 54

Abstract:

In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K−2, the number of instructions issued for cycle K−1 and the number of instructions speculatively issued in cycle K−1 that have produced a cache hit, and subtracting from the sum the number of instructions enqueued for cycle K−1. The result indicates the number of invalid instructions in the queue cycle K. The number of invalid entries instructions, the number of issued instructions, and the number of enqueued instructions are preferably represented as flat vectors, so that adding is performed by shifting in one direction, while subtracting is performed by shifting in the opposite direction. The result is compared with either the number of instructions to be enqueued in the present cycle, which number is encoded, or with a predetermined value. A stall signal is generated if the indicative value is less than the encoded number or the predetermined value.

US Patent:

20050038979, Feb 17, 2005

Filed:

Sep 21, 2004

Appl. No.:

10/945710

Inventors:

Timothy Fischer - Maynard MA, US
Daniel Leibholz - Cambridge MA, US
James Farrell - Harvard MA, US

International Classification:

G06F009/30

US Classification:

712214000

Abstract:

In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K-, the number of instructions issued for cycle K-and the number of instructions speculatively issued in cycle K-that have produced a cache hit, and subtracting from the sum the number of instructions enqueued for cycle K-. The result indicates the number of invalid instructions in the queue cycle K. The number of invalid entries instructions, the number of issued instructions, and the number of enqueued instructions are preferably represented as flat vectors, so that adding is performed by shifting in one direction, while subtracting is performed by shifting in the opposite direction. The result is compared with either the number of instructions to be enqueued in the present cycle, which number is encoded, or with a predetermined value. A stall signal is generated if the indicative value is less than the encoded number or the predetermined value.

US Patent:

50141953, May 7, 1991

Filed:

May 10, 1990

Appl. No.:

7/522503

Inventors:

James A. Farrell - Marlboro MA
Richard L. Sites - Boylston MA

Assignee:

Digital Equipment Corporation, Inc. - MA

International Classification:

G11C 1300

US Classification:

364200

Abstract:

A set associative cache using decoded data element select lines which can be selectively configured to provide different data sets arrangements. The cache includes a tag array, a number of tag comparators corresponding to the maximum possible number of sets, a data element select logic circuit, and a data array. The tag and data arrays each provide, in response to an input address, a number of output tag and data elements, respectively. The number of output tag and data elements depends upon the maximum set size desired for the cache. An input main memory address is used to address both the tag and data arrays. The tag comparators compare a tag field portion of the input main memory address to each element output from the tag array. The select logic then uses the outputs of the tag comparators and one or more of the input main memory address bits to generate decoded data array enable signals. The decoded enable signals are then coupled to enable the desired one of the enabled data elements.

US Patent:

RE307297, Sep 1, 1981

Filed:

May 30, 1978

Appl. No.:

5/910513

Inventors:

James H. Farrell - Lexington MA
Ralph A. Bianchi - Lexington MA
Edward E. Johanson - Andover MA

Assignee:

JBF Scientific Corporation - Wilmington MA

International Classification:

B01D 2100

US Classification:

210801

Abstract:

Apparatus and method for removing floating material from the surface of a body of liquid and for collecting the material has an endless belt-type materials transport mounted, as by rollers with vertically-separated horizontal rotation axes, to dispose the transport with a lower flight inclined downwardly from above the liquid surface at a frontal location to below the surface at a rearward location. A collection well is contiguously behind the rearward location. The transport is driven to advance the lower flight in the direction from the frontal location to the rearward location. This motion carries floating material from the liquid surface downward and rearward under the lower flight of the transport and releases it at the rearward location to float upward into the collection well. A method for floatage collection by steps that the foregoing apparatus performs is also disclosed. BACKGROUND.