James J Farrell

US Patent:

6405304, Jun 11, 2002

Filed:

Aug 24, 1998

Appl. No.:

09/138957

Inventors:

James Arthur Farrell - Harvard MA
Sharon Marie Britton - Westboro MA
Bruce Gieseke - San Jose CA
Daniel Lawrence Leibholz - Cambridge MA
Derrick R. Meyer - Austin TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 1500

US Classification:

712216, 712 23, 712217, 712218, 712219, 712233, 712237, 712240, 712244

Abstract:

A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of register assignments that assign logical registers to the physical registers. The technique further involves maintaining, in a vector memory circuit having bits that respectively correspond to the physical registers, a valid vector that forms, in combination with the list of register assignments, a list of valid register assignments. Furthermore, the technique involves storing, for an instruction that is mapped by the data processor, a copy of the valid vector from the vector memory circuit to a silo memory circuit. Preferably, the processor using the technique has the ability to execute branches of instructions speculatively, and to recover if it is determined that the processor executed down an incorrect instruction branch.

US Patent:

6438732, Aug 20, 2002

Filed:

Apr 14, 1999

Appl. No.:

09/291345

Inventors:

James Arthur Farrell - Harvard MA
Nevine Nassif - Arlington MA
Gill Watt - Acton MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1750

US Classification:

716 4, 716 5, 716 6

Abstract:

A method and apparatus for determining load capacitance of DCVSL circuits in timing verification of a circuit is disclosed in the present invention. The gate capacitances for various MOS devices are modeled based upon simulations with certain conditions for inputs to the gate, source and drain. The system then determines the existence of DCVSL circuits within the topology of a circuit, and applies one of several models to determine minimum and maximum capacitances for the encountered DCVSL structures. The determination of minimum and maximum capacitance depends upon the selected model and the capacitance of each of the MOS devices as previously calculated.

US Patent:

6473888, Oct 29, 2002

Filed:

Dec 10, 1998

Appl. No.:

09/208780

Inventors:

Nevine Nassif - Arlington MA
Madhav Desai - Mumbai, IN
James Arthur Farrell - Harvard MA
Roy Badeau - Berlin MA
Nicholas Lee Rethman - North Andover MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1750

US Classification:

716 6, 716 5, 716 4

Abstract:

The present invention relates to a method and apparatus for determining capacitance and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

US Patent:

6542987, Apr 1, 2003

Filed:

Dec 17, 1999

Appl. No.:

09/465689

Inventors:

Timothy Charles Fischer - Maynard MA
Daniel Lawrence Leibholz - Cambridge MA
James Arthur Farrell - Harvard MA

Assignee:

Hewlett-Packard Development Company L.P. - Houston TX

International Classification:

G06F 930

US Classification:

712217, 712219, 712245, 714 21

Abstract:

In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K-2, the number of instructions issued for cycle K-1 and the number of instructions speculatively issued in cycle K-1 that have produced a cache hit, and subtracting from the sum the number of instructions enqueued for cycle K-1. The result indicates the number of invalid instructions in the queue cycle K. The number of invalid entries instructions, the number of issued instructions, and the number of enqueued instructions are preferably represented as flat vectors, so that adding is performed by shifting in one direction, while subtracting is performed by shifting in the opposite direction. The result is compared with either the number of instructions to be enqueued in the present cycle, which number is encoded, or with a predetermined value. A stall signal is generated if the indicative value is less than the encoded number or the predetermined value.

US Patent:

6658506, Dec 2, 2003

Filed:

Apr 14, 1999

Appl. No.:

09/292051

Inventors:

Nevine Nassif - Arlington MA
James Arthur Farrell - Harvard MA
Dale Hayward Hall - Northborough MA
Gill Watt - Acton MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 104

US Classification:

710 58, 713500, 455114, 375296

Abstract:

A system for accurately determining Elmore delays in DCVSL structures is disclosed. The system uses circuit simulation to determine models for Elmore delays through devices within specific circuit structures. The circuit structures include DCVSL circuits to accurately model performance of devices with such a structure. The system also determines discharge characteristics for DCVSL circuits using simulation. In order to determine Elmore delays, the system analyzes a circuit representation to locate DCVSL structures. The discharge characteristics and models are used to determine Elmore delays for each structure located.

US Patent:

6675288, Jan 6, 2004

Filed:

May 9, 2002

Appl. No.:

10/144097

Inventors:

James Arthur Farrell - Harvard MA
Sharon Marie Britton - Westboro MA
Bruce Gieseke - San Jose CA
Daniel Lawrence Leibholz - Cambridge MA
Derrick R. Meyer - Austin TX

Assignee:

Hewlett-Packard Development Company L.P. - Houston TX

International Classification:

G06F 1500

US Classification:

712216, 712 23, 712217, 712218, 712219, 712233, 712237, 712240, 712244

Abstract:

A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of register assignments that assign logical registers to the physical registers. The technique further involves maintaining, in a vector memory circuit having bits that respectively correspond to the physical registers, a valid vector that forms, in combination with the list of register assignments, a list of valid register assignments. Furthermore, the technique involves storing, for an instruction that is mapped by the data processor, a copy of the valid vector from the vector memory circuit to a silo memory circuit. Preferably, the processor using the technique has the ability to execute branches of instructions speculatively, and to recover if it is determined that the processor executed down an incorrect instruction branch.

US Patent:

6704856, Mar 9, 2004

Filed:

Dec 17, 1999

Appl. No.:

09/465175

Inventors:

James A. Farrell - Harvard MA
Timothy C. Fischer - Maynard MA
Daniel L. Leibholz - Cambrdige MA
Bruce A. Gieseke - Ashland MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 930

US Classification:

712215, 712217, 712218, 712 23

Abstract:

A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each row, multiplexor select signals are generated from the flat vector counts for the N rows above and including the present row, and from the validity indicators associated with the N rows, where N is a predetermined value. A multiplexor associated with a particular row selects one of the N rows according to the select value, and moves or passes the instruction held in the selected row to the present row. A rows select value is determined by forming a diagonal from the N count vectors corresponding to the N rows above and including the present row, and logically ANDing, each diagonal bit with the valid bit associated with the same row. Each rows count vector is determined in two stages. In the first stage, a local count is determined for each row in a local group of rows, and a global count is determined for the entire local group.

US Patent:

6877142, Apr 5, 2005

Filed:

Aug 13, 2002

Appl. No.:

10/218079

Inventors:

Nevine Nassif - Arlington MA, US
Madhav Desai - Mumbai, IN
James Arthur Farrell - Harvard MA, US
Roy Badeau - Berlin MA, US
Nicholas Lee Rethman - North Andover MA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F017/50

US Classification:

716 6, 716 4, 716 5

Abstract:

The present invention relates to a method and apparatus for determining capacitances and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

Address:

265 Cocoplum Ddrive Nort, Jupiter, FL 33458

Phone:

5618898733

VIN:

2HNYD2H3XCH524834

Make:

ACURA

Model:

MDX

Year:

2012