James D Fitzpatrick

US Patent:

20020069115, Jun 6, 2002

Filed:

Dec 1, 2000

Appl. No.:

09/726561

Inventors:

James Fitzpatrick - Newport Beach CA, US

Assignee:

Catalina Marketing International, Inc. - St. Petersburg FL

International Classification:

G06F017/60

US Classification:

705/026000

Abstract:

A method, system and computer program product for online shopping. The system on which the method and computer program product are based determines a shopping district for a customer based on customer-derived information, generates a present order list of at least one item to price, selects from a global database of retailers those selected retailers within the shopping district selling the items, and forms a selection list of the selected retailers. The list indicates the price and availability of the items on the selection list. A shopping basket including selected items and prices of the selected items is determined from the list of selected retailers. A to-be-purchased list is formed for at least a part of the shopping basket list which the customer confirms. The to-be-purchased list is used to generate purchase coupons for redemption at a confirmed retailer. Alternatively, the to-be-purchased list is direct ordered from each confirmed retailer.

US Patent:

20030088466, May 8, 2003

Filed:

Dec 7, 2000

Appl. No.:

09/730592

Inventors:

James Fitzpatrick - Newport Beach CA, US

Assignee:

Catalina Marketing International, Inc. - St. Petersburg FL

International Classification:

G06F017/60

US Classification:

705/014000

Abstract:

A novel price paid database, method, system, and computer program product in which checkout items are scanned at a plurality of stores, and a checkout computer identifies the purchased items. The checkout computer determines a price paid for each purchased item. A central computer records in a price-paid database an item identification and price-paid for each purchased items. The central computer publishes the price-paid database. The checkout computer recurrently updates the price-paid database in the central computer with the price paid for each purchased item, the customer identification (if available), the store identification, and a list price for each purchased item.

US Patent:

20220300428, Sep 22, 2022

Filed:

Mar 2, 2022

Appl. No.:

17/685250

Inventors:

- Boise ID, US
James Fitzpatrick - Laguna Niguel CA, US

International Classification:

G06F 12/0882
G06F 12/0811
G11C 11/56
G06F 12/02

Abstract:

A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.

US Patent:

20220270686, Aug 25, 2022

Filed:

May 11, 2022

Appl. No.:

17/742345

Inventors:

- Boise ID, US
James Fitzpatrick - Laguna Niguel CA, US
Patrick Robert Khayat - San Diego CA, US
Sivagnanam Parthasarathy - Carlsbad CA, US

International Classification:

G11C 16/26
G11C 29/50
G11C 11/56

Abstract:

A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

US Patent:

20220246214, Aug 4, 2022

Filed:

Apr 20, 2022

Appl. No.:

17/724940

Inventors:

- Boise ID, US
James Fitzpatrick - Laguna Niguel CA, US
Kishore Kumar Muchherla - Fremont CA, US

International Classification:

G11C 16/10
G06F 3/06
G11C 11/56
G11C 16/26

Abstract:

A memory system to store multiple bits of data in a memory cell. A memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. The threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. A group identification of a first group, among the groups, containing the first level is determined for the memory cell. The memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. The data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell.

US Patent:

20220199154, Jun 23, 2022

Filed:

Dec 18, 2020

Appl. No.:

17/127459

Inventors:

- Boise ID, US
James Fitzpatrick - Laguna Niguel CA, US
Kishore Kumar Muchherla - Fremont CA, US

International Classification:

G11C 11/56
G11C 16/10
G11C 16/26

Abstract:

A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of values of the data bits according to a mapping between combinations of values of bits and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. XOR (or XNOR) is used to combine the data bits into bits of a group identification of a first group, among the plurality of groups, that contains the first level. The memory device reads, using the group identification, the data bits back from the first memory cell to finely program the threshold voltage of the memory cell to represent the data bits.

US Patent:

20220199165, Jun 23, 2022

Filed:

Dec 18, 2020

Appl. No.:

17/247643

Inventors:

- Boise ID, US
James Fitzpatrick - Laguna Niguel CA, US
Kishore Kumar Muchherla - Fremont CA, US

International Classification:

G11C 16/20
G11C 16/26
G11C 16/30

Abstract:

Control logic in a memory device identifies a first plurality of groups of programming distributions, wherein each group comprises a subset of programming distributions associated with a portion of a memory array of the memory device configured as quad-level (QLC) memory. During a first pass of a multi-pass programming operation, the control logic coarsely programs memory cells in the portion configured as QLC memory to initial values representing a second plurality of pages of host data and stores, in a portion of the memory array of the memory device configured as single-level cell (SLC) memory, an indicator of the first plurality of groups of programming distributions with which each of the coarsely programmed memory cells is associated. During a second pass of the multi-pass programming operation, the control logic reads the coarsely programmed initial values from the first pass based on the indicator of the first plurality of groups of programming distributions and finely programs the memory cells in the portion configured as QLC memory to final values representing the second plurality of pages of host data.

US Patent:

20220199172, Jun 23, 2022

Filed:

Dec 18, 2020

Appl. No.:

17/127413

Inventors:

- Boise ID, US
James Fitzpatrick - Laguna Niguel CA, US
Kishore Kumar Muchherla - Fremont CA, US

International Classification:

G11C 16/34
G11C 16/10
G11C 16/26
G11C 16/30

Abstract:

In a coarse programming, the threshold voltage of the memory cell is programmed to a first level representative of N−1 bit values data according to a first mapping between combinations of values of N−1 possible bits and threshold levels. A group identification is representative of whether the first level is an odd or even numbered level in the first mapping. For a fine programming, the memory cell is read, based on the group identification, to obtain the N−1 bit values; and at least one additional bit is received to join the N−1 bit values to form at least N bit values. The threshold voltage of the memory cell is then finely programmed to a second level representative of the at least N bit values according to a second mapping between combinations of values of the at least N possible bits and threshold levels.