James Scott Harveland

US Patent:

6816023, Nov 9, 2004

Filed:

Jun 12, 2003

Appl. No.:

10/460592

Inventors:

Guy Richard Currier - Rochester MN
James Scott Harveland - Byron MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03B 100

US Classification:

331 74, 331 2, 331 46, 331 49

Abstract:

An oscillator transmission switching circuit switches between asynchronous oscillator signals with low latency. Preferably, a fast switching circuit triggers a transition from a first oscillator to a second oscillator by entering a bridge input immediately following an edge of the first oscillator, holding in the bridge input until the same edge of the second oscillator is detected, and switching to the second oscillator. Preferably, the bridge input is selectable to accommodate conditions in which the first oscillator signal is stuck at either a logic 0 or a logic 1. A change of oscillators may be triggered by a fault detection circuit or by an external signal.

US Patent:

20090063894, Mar 5, 2009

Filed:

Aug 29, 2007

Appl. No.:

11/846783

Inventors:

Ronald L. Billau - Rochester MN, US
John D. Folkerts - Rochester MN, US
Ross L. Franke - Fochester MN, US
James S. Harveland - Byron MN, US
Brian G. Holthaus - Oronoco MN, US

International Classification:

G06F 11/07
G06F 13/00
G06F 13/14

US Classification:

714 5, 710104, 710305, 714E11112

Abstract:

A system with an autonomic PCI Express hardware detection and failover mechanism includes a plurality of combination root complex capable and endpoint capable devices. A combination root complex capable and endpoint capable device may be selectively configured to operate in either a root complex mode or an endpoint mode. One of the devices assumes the root complex mode and the remaining devices each assume the endpoint mode. Each of the endpoint mode devices is adapted to detect a failure of the root complex mode device. In response to detection of the failure of the root complex mode device, one of the endpoint mode devices assumes root complex mode. An endpoint device may include a timer with a timeout value. Whenever, an endpoint device receives a communication from the root complex device, the endpoint device restarts its timer. If the timer times out with the endpoint device receiving a communication from the root complex device, the endpoint device issues a read request to the root complex device. If the root complex device does not respond to the read request, the endpoint device assumes root complex mode. Different endpoint devices may be assigned different timeout values. Accordingly, the endpoint device that is assigned the shortest time out value will assume root complex mode upon detection of a root complex device failure.

US Patent:

6684362, Jan 27, 2004

Filed:

Feb 18, 1999

Appl. No.:

09/251032

Inventors:

Guy Richard Currier - Rochester MN
James Scott Harveland - Rochester MN
Sharon Denos Vincent - Rochester MN
Paul Leonard Wiltgen - Kasson MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 1300

US Classification:

714758

Abstract:

Methods and apparatus are provided for connecting a manufacturing test interface to a global serial bus, such as an inter integrated circuit (I C) bus. Input/output buffer logic buffers data to be transferred to and from the global serial bus. A slave interface logic connected to the input/output buffer logic receives and sends data to the input/output buffer logic. A slave controller coupled to the input/output buffer logic and the slave interface logic paces data exchange to the input/output buffer logic. Error detection logic is coupled between the input/output buffer and the global serial bus for detecting error conditions.