James R Heath

US Patent:

6459095, Oct 1, 2002

Filed:

Mar 29, 1999

Appl. No.:

09/282048

Inventors:

James R. Heath - Santa Monica CA
R. Stanley Williams - Mountain View CA
Philip J. Kuekes - Menlo Park CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H01L 2906

US Classification:

257 14

Abstract:

A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.

US Patent:

6756296, Jun 29, 2004

Filed:

Dec 11, 2001

Appl. No.:

10/015063

Inventors:

James R. Heath - Santa Monica CA
Charles P. Collier - San Marino CA
Yi Luo - Los Angeles CA
Erica DeIonno - Los Angeles CA
Patricia A. Beck - Palo Alto CA

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H01L 214763

US Classification:

438622

Abstract:

Methods for making electronic devices where a molecular monolayer or multilayer is sandwiched between top and bottom electrodes at electrode intersections. The molecular layer has an electrical characteristic such as bistable switching. A layer of electrically conductive material is used to protect the molecular layer during formation of the top electrode pattern. The electrically conductive material remains sandwiched between the top and bottom electrodes at the electrode intersections in the final electronic device.

US Patent:

6846682, Jan 25, 2005

Filed:

Jul 17, 2001

Appl. No.:

09/907314

Inventors:

James R. Heath - Santa Monica CA, US
R. Stanley Williams - Mountain View CA, US
Philip J. Kuekes - Menlo Park CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L 2100

US Classification:

438 2

Abstract:

A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.

US Patent:

6903366, Jun 7, 2005

Filed:

Oct 31, 2003

Appl. No.:

10/699172

Inventors:

James R. Heath - Santa Monica CA, US
R. Stanley Williams - Mountain View CA, US
Philip J. Kuekes - Menlo Park CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L029/06

US Classification:

257 14, 257 40

Abstract:

A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.

US Patent:

6979639, Dec 27, 2005

Filed:

Mar 16, 2004

Appl. No.:

10/803119

Inventors:

James R. Heath - Los Angeles CA, US
Charles P. Collier - Los Angeles CA, US
Yi Luo - Los Angeles CA, US
Erica DeIonno - Los Angeles CA, US
Patricia A. Beck - Palo Alto CA, US

Assignee:

California Institute of Technology - Pasadena CA
Hewlett-Packard Development Co., L.P. - Houston TX

International Classification:

H01L021/4763

US Classification:

438622, 438623

Abstract:

Methods for making electronic devices where a molecular monolayer or multilayer is sandwiched between top and bottom electrodes at electrode intersections. The molecular layer has an electrical characteristic such as bistable switching. A layer of electrically conductive material is used to protect the molecular layer during formation of the top electrode pattern. The electrically conductive material remains sandwiched between the top and bottom electrodes at the electrode intersections in the final electronic device.

US Patent:

7161168, Jan 9, 2007

Filed:

Jul 28, 2003

Appl. No.:

10/521714

Inventors:

James R. Heath - South Pasadena CA, US
Pierre M. Petroff - Santa Barbara CA, US
Nicholas A. Melosh - Menlo Park CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

H01L 29/06

US Classification:

257 9, 438200, 438197, 977762, 977760, 977847, 977938, 257E33009, 257E29072, 257 15

Abstract:

Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate.

US Patent:

7169696, Jan 30, 2007

Filed:

Jun 22, 2004

Appl. No.:

10/875057

Inventors:

James R. Heath - South Pasadena CA, US
Yi Luo - Pasadena CA, US
Rob Beckman - Los Angeles CA, US

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H01L 21/4763

US Classification:

438618, 438637, 438647, 438657

Abstract:

A system and method for selecting nanometer-scaled devices. The method includes a plurality of semiconductor wires. Two adjacent semiconductor wires of the plurality of semiconductor wires are associated with a separation smaller than or equal to 100 nm. Additionally, the system includes a plurality of address lines. Each of the plurality of address lines includes a gate region and an inactive region and intersects the plurality of semiconductor wires at a plurality of intersections. The plurality of intersections includes a first intersection and second intersection. The first intersection is associated with the gate region, and the second intersection is associated with the inactive region.

US Patent:

7416911, Aug 26, 2008

Filed:

Jun 23, 2004

Appl. No.:

10/876276

Inventors:

James R. Heath - South Pasadena CA, US
Yuri Bunimovich - Los Angeles CA, US
Guanglu Ge - Pasadena CA, US
Kristen Beverly - Pasadena CA, US
John Nagarah - Los Angeles CA, US
Michael Roukes - Pasadena CA, US
Peter Willis - Los Angeles CA, US

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H01L 21/306

US Classification:

438 49, 977704, 977762, 977792, 977794, 977830, 977899, 977920, 977924, 977958

Abstract:

A method by which silicon nanostructures may be selectively coated with molecules or biomolecules using an electrochemical process. This chemical process may be employed as a method for coating many different nanostructures within a circuit, each with a different molecular or biomolecular material. The density of devices within a circuit of devices that can be coated with different molecules is limited only by the ability to electronically address each device separately. This invention has applications toward the fabrication of molecular electronic circuitry and toward the fabrication of nanoelectronic molecular sensor arrays.