James Matt Hellums

US Patent:

6346851, Feb 12, 2002

Filed:

Nov 22, 2000

Appl. No.:

09/718716

Inventors:

Zhengwei Zhang - Plano TX
James R. Hellums - Plano TX
John M. Muza - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 500

US Classification:

327558, 327552, 327553, 327336

Abstract:

A low-pass filter circuit includes: a first compound transistor device ( ) and ( ) coupled between an input node ( ) and an output node ( ); a first transistor ( ) coupled to the input node ( ), a gate of the first transistor ( ) is coupled to a drain of the first transistor ( ); a second compound transistor device ( ) and ( ) coupled between a gate of the first compound transistor device ( ) and ( ) and the gate of the first transistor ( ); a second transistor ( ) coupled to the first transistor ( ) and having a gate coupled to a gate of the second compound transistor device ( ) and ( ), the gate of the second transistor ( ) is coupled to a drain of the second transistor ( ); a current source ( ) coupled to the drain of the second transistor ( ); a first capacitor (C ) coupled to the output node ( ); and a second capacitor (C ) coupled to the gate of the first compound transistor device ( ) and ( ).

US Patent:

6384664, May 7, 2002

Filed:

Oct 5, 2000

Appl. No.:

09/680811

Inventors:

James R. Hellums - Plano TX
Baher Haroun - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01H 8500

US Classification:

327525, 327526

Abstract:

A differential voltage sense circuit has a fuse placed in one upper leg of a resistance bridge while the remaining upper leg (sense leg) employs a resistor constructed of doped poly or poly silicide or constructed of the doped silicon that forms the N-well or P-well in CMOS process. The lower legs each have a switch selected from a pair of matched switches. A comparator, latch and combinational logic sense the state of the fuse in the resistance bridge and latch the state information before the switches can operate to stop the flow of current in the resistance bridge. The differential voltage sense circuit can operate at low voltage levels compatible with advanced CMOS processes.

US Patent:

6413824, Jul 2, 2002

Filed:

Jun 8, 2000

Appl. No.:

09/589953

Inventors:

Amitava Chatterjee - Plano TX
Alec J. Morton - Plano TX
Mark S. Rodder - University Park TX
Taylor R. Efland - Richardson TX
Chin-Yu Tsai - Plano TX
James R. Hellums - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218234

US Classification:

438275, 438232, 438279, 438286

Abstract:

High performance digital transistors ( ) and analog transistors ( ) are formed at the same time. The digital transistors ( ) include pocket regions ( ) for optimum performance. These pocket regions ( ) are partially or completely suppressed from at least the drain side of the analog transistors ( ) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors ( ).

US Patent:

6671663, Dec 30, 2003

Filed:

Jun 24, 1998

Appl. No.:

09/103704

Inventors:

James R. Hellums - Plano TX
James R. Hochschild - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1750

US Classification:

703 14, 703 2, 702 57, 702117, 702190, 716 4

Abstract:

A circuit simulator is provided for simulating the operation of a circuit in the time domain by accounting for the physical fluctuation (noise) in the time domain. Each of the components ( ) in the matrix ( ) has associated therewith an active current generator which can be simulated by the simulator in the time domain. In parallel with this active current generator, a stochastic (random) process current generator is provided. This stochastic current generator for each element will utilize a Gaussian random number generator (with 0 mean and a variance equal to 1) that is scaled by the standard deviation (square root of the variance) of the physical noise process that exists within the device. Additionally, this Gaussian random number generator is scaled by a factor that accounts for the time step or discrete operation of the noise simulator.

US Patent:

6741129, May 25, 2004

Filed:

Dec 19, 2002

Appl. No.:

10/324271

Inventors:

Marco Corsi - Parker TX
James R. Hellums - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 345

US Classification:

330252, 330254, 327359

Abstract:

A fully differential amplifier slew rate boosting scheme for use with an amplifier having a closed-loop gain very near unity or less has the first plates of the compensation capacitors and conventionally coupled to internal high impedance gain nodes and , but has the other plates of the compensation capacitors and unconventionally driven with the input signal IN+ and IN-. The voltages appearing across the compensation capacitors and in response to changes in the input signal is significantly less than that achieved using conventional compensation architectures where the other plates of the compensation capacitors are coupled to ground. Since little current is now required to charge the compensation capacitors and , the input stage tail current no longer limits the slew rate.

US Patent:

7777569, Aug 17, 2010

Filed:

Jan 21, 2009

Appl. No.:

12/357221

Inventors:

James R. Hellums - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 3/45

US Classification:

330255, 330253, 330261

Abstract:

A method for actuating an amplifier to generally eliminate a pop is provided. Accordingly, a plurality of current sources is actuated in an input stage, and a plurality of bias voltages are applied to the input stage. After a predetermined period after the step of applying a plurality of bias voltages to the input stage and the step of actuating a plurality of current sources in an input stage, a control circuit is actuated, and a transistor within a control amplifier stage is turned on at a predetermined rate.

US Patent:

7915882, Mar 29, 2011

Filed:

Aug 28, 2008

Appl. No.:

12/199942

Inventors:

James R. Hellums - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 3/08
G05F 3/16

US Classification:

323312, 323313, 323314, 323315

Abstract:

A current reference circuit is disclosed. A small startup current is defined as the base current into a bipolar transistor with its collector-emitter path connected in series with a resistor between the power supply voltage and ground. This startup current is conducted via a diode-connected MOS transistor in a first leg of a current mirror. Temperature compensation is maintained by a reference leg in the current mirror that includes a bipolar transistor having an emitter area N times larger than that of a bipolar transistor in a second leg of the current mirror, to establish a temperature-compensated current in the reference leg. A compensation capacitor connected between the collector and base of a bipolar transistor in the first leg suppresses oscillation, and can be modest in size due to the Miller effect.

US Patent:

20090201001, Aug 13, 2009

Filed:

Dec 15, 2008

Appl. No.:

12/335164

Inventors:

Shanmuganand Chellamuthu - Richardson TX, US
James R. Hellums - Plano TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

G05F 1/10

US Classification:

323282

Abstract:

A switching mode power supply utilizing an analog sampled data system in the feedback control loop in which the coefficients of the sampled data system are change by reprogramming a programmable nonvolatile memory when external LC values vary.