James R Henson

US Patent:

58729020, Feb 16, 1999

Filed:

Jun 19, 1995

Appl. No.:

8/492393

Inventors:

Roman Kuchkuda - San Diego CA
John Rigg - Poway CA
Manuel Rey Enriquez - Oceanside CA
James V. Henson - Poway CA
Curt Stehley - Solana Beach CA

Assignee:

Nihon Unisys, Ltd. - Tokyo

International Classification:

G06T 1140

US Classification:

395130

Abstract:

A system for rendering visual images that combines sophisticated anti-aliasing and pixel blending techniques with control pipelining in hardware embodiment. A highly-parallel rendering pipeline performs sophisticated polygon edge interpolation, pixel blending and anti-aliasing rendering operations in hardware. Primitive polygons are transformed to subpixel coordinates and then sliced and diced to create "pixlink" elements mapped to each pixel. An oversized frame buffer memory allows the storage of many pixlinks for each pixel. Z-sorting is avoided through the use of a linked-list data object for each pixlink vector in a pixel stack. Because all image data values for X, Y, Z, R, G, B and pixel coverage A are maintained in the pixlink data object, sophisticated blending operations are possible for anti-aliasing and transparency. Data parallelism in the rendering pipeline overcomes the processor efficiency problem arising from the computation-intensive rendering algorithms used in the system of this invention. Single state machine control is made possible through linked data/control pipelining.

US Patent:

20160139639, May 19, 2016

Filed:

Nov 18, 2014

Appl. No.:

14/546914

Inventors:

- Amsterdam, NL
James V. Henson - Poway CA, US
Bhasker R. Jakka - San Diego CA, US

International Classification:

G06F 1/26
G06F 11/10
G06F 1/32
G06F 3/06

Abstract:

In general, techniques are described for resource allocation and deallocation that facilitates power management. A device comprising one or more processors and a memory may be configured to perform the techniques. The processor may be configured to determine usage of a first non-zero subset of a plurality of resources, the plurality of resources allocated and released in accordance with a thermometer data structure. The processors may further be configured to compare the usage of the first non-zero subset of the plurality of resources to a threshold separating the first non-zero subset of the plurality of resources from a second non-zero subset of the plurality of resources, and power on the second non-zero subset of the plurality of resources based at least on the comparison. The memory may be configured to store the threshold.