James K Holt

US Patent:

7383393, Jun 3, 2008

Filed:

Oct 28, 2005

Appl. No.:

11/261357

Inventors:

Hassan F. Al Sukhni - Austin TX, US
James C. Holt - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 12/00

US Classification:

711137

Abstract:

A first prefetch engine from a first plurality of prefetch engines is allocated to a first load instruction in response to a buffer miss of an iteration of the first load instruction in a program stream. The first plurality of prefetch engines include prefetch engines for prefetching data from memory to a buffer based on a predicted stride. A second prefetch engine from a second plurality of prefetch engines is allocated to the first load instruction in response to the buffer miss. The second plurality of prefetch engines include prefetch engines for prefetching data from memory to the buffer based on an instruction loop representative of a sequence of instructions that affect an address value associated with an allocated load instruction. One of the first or second prefetch engines is deallocated if the other prefetch engine achieves a prefetch performance greater than a first threshold value.

US Patent:

7506105, Mar 17, 2009

Filed:

May 2, 2005

Appl. No.:

11/120288

Inventors:

Hassan F. Al-Sukhni - Austin TX, US
James C. Holt - Austin TX, US
Matt B. Smittle - Allen TX, US
Michael D. Snyder - Austin TX, US
Brian C. Grayson - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 12/06
G06F 9/34

US Classification:

711137, 711216, 711217, 712207

Abstract:

Generating a hashed value of the program counter in a data processing system. The hashed value can be used for prefetching in the data processing system. In some examples, the hashed value is used to identify whether a load instruction associated with the hashed value has an address that is part of a strided stream in an address stream. In some examples, the hashed value is a subset of bits of the bits of the program counter. In other examples, the hashed value may be derived in other ways from the program counter.

US Patent:

8340952, Dec 25, 2012

Filed:

Mar 12, 2009

Appl. No.:

12/403156

Inventors:

Puneet Sharma - Austin TX, US
James C. Holt - Austin TX, US
Kamal S. Khouri - Austin TX, US
Hassan Al Sukhni - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50

US Classification:

703 13, 703 14

Abstract:

A set of instructions executable at an integrated circuit is partitioned into multiple instruction blocks. A first and second instruction block are executed multiple times, including a first execution and a second execution. The first execution of the first instruction block is associated with a first set of executions, and the first execution of the second instruction block is associated with a second set of executions. A first amount of energy consumption representative of a member of the first set of executions is determined, and a second amount of energy consumption representative of a member of the second set of executions is determined. The first amount of energy is assigned to each member of the first set, and the second amount of energy is assigned to each member of the second set, and used to determine a total amount of energy consumption associated with execution of the set of instructions.

US Patent:

20050034042, Feb 10, 2005

Filed:

Dec 31, 2003

Appl. No.:

10/750351

Inventors:

Mark Davies - Austin TX, US
Stephen Louton - Bee Cave TX, US
Timothy Pletcher - Austin TX, US
James Holt - Austin TX, US
Daniel Walters - Austin TX, US

International Classification:

G06F011/00
G01R031/28

US Classification:

714736000

Abstract:

A system and method for determining mismatched or faulty data records in a telecommunications or other system containing large data sets from records in first and second data sets identifies potentially mismatched or faulty data records in the first data set at least in part by comparing records in the first data set to records in the second data set. The potentially mismatched or faulty records identified as potentially mismatched or faulty are verified as defective using at least one predetermined criteria.

US Patent:

20060248279, Nov 2, 2006

Filed:

May 2, 2005

Appl. No.:

11/120272

Inventors:

Hassan Al-Sukhni - Austin TX, US
Brian Grayson - Austin TX, US
James Holt - Austin TX, US
Matt Smittle - Allen TX, US
Michael Snyder - Austin TX, US

International Classification:

G06F 13/00

US Classification:

711137000, 711111000

Abstract:

Prefetching across a page boundary in a data processing system. The system determines whether a prefetch will cross a page boundary of memory, and if so, it determines whether a translation source has an entry corresponding to the virtual address of the prefetch. If the translation source has an entry corresponding the virtual address, a physical address of the virtual address is used to prefetch the information.

US Patent:

20060248280, Nov 2, 2006

Filed:

May 2, 2005

Appl. No.:

11/120287

Inventors:

Hassan Al-Sukhni - Austin TX, US
James Holt - Austin TX, US
Jyotsna Kartha - Round Rock TX, US
Michael Snyder - Austin TX, US

International Classification:

G06F 13/00

US Classification:

711137000

Abstract:

Adjusting the confidence level of prefetch circuitry in generating outstanding prefetch address of a detected strided stream. In one example, the number of outstanding prefetches allowed is adjusted based on a determination of whether a prefetch to a prefetch address is used in a data processing system. With some systems, the higher the confidence level, the more outstanding prefetches are allowed.

US Patent:

20070101100, May 3, 2007

Filed:

Oct 28, 2005

Appl. No.:

11/262171

Inventors:

Hassan Al Sukhni - Austin TX, US
James Holt - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 9/30

US Classification:

712207000

Abstract:

A program stream is executed at a first processing engine, the program stream including multiple iterations of a first load instruction. An instruction loop is executed at a second processing engine separate from the first processing engine substantially in parallel with an execution of the program stream at the first processing engine for prefetching data from memory to a buffer for one or more iterations of the first load instruction of the program stream. The instruction loop represents a subset of a sequence of instructions between iterations of the first load instruction that affect an address value associated with the first load instruction. A confidence value associated with the instruction loop is modified based on a prefetch performance of one or more iterations of the first load instruction and it is determined whether to terminate execution of the instruction loop based on the confidence value.

US Patent:

54486840, Sep 5, 1995

Filed:

Nov 12, 1993

Appl. No.:

8/150295

Inventors:

James C. Holt - Del Valle TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1500

US Classification:

395 24

Abstract:

A neuron (100) has a null-inhibiting function so that null inputs do not affect the output of the neuron (100) or updating of its weights. The neuron (100) provides a net value based on a sum of products of each of several inputs, and corresponding weight and null values, and provides an output in response to the net value. A neural network (40) which uses such a neuron (100) has a first segmented layer (41) in which each segment (50-52) corresponds to a manufacturing process step (60-62). Each segment of the first layer (41) receives as inputs measured values associated with the process step (60-62). A second layer (42) connected to the first layer (4l), is non-segmented to model the entire manufacturing process (80). The first (41) and second (42) layers are both unsupervised and competitive. A third layer (43) connected to the second layer (42) then estimates parameters of the manufacturing process (80) and is unsupervised and noncompetitive.

Address:

7309 Mitra Dr, Austin, TX 78739

Phone:

5123014905

VIN:

JM1BK32F991214515

Make:

MAZDA

Model:

MAZDA3

Year:

2009