James M Huffman

US Patent:

6344672, Feb 5, 2002

Filed:

May 30, 2001

Appl. No.:

09/870285

Inventors:

James D. Huffman - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27108

US Classification:

257296, 257297, 257313

Abstract:

An improved memory cell ( ) for use in a high-intensity light environment. The memory ( ) comprises a substrate ( ) capable of generating photocarriers when exposed to radiant energy, at least one transistor ( ), at least one capacitor ( ), and address node ( ) electrically connecting the transistor ( ) and the capacitor ( ), and an active collector region ( ). The active collector region ( ) is fabricated in the substrate ( ) in a position to allow the active collector region ( ) to recombine photocarriers traveling through the substrate ( ) thus preventing the photocarriers from reaching the address node ( ).

US Patent:

6414515, Jul 2, 2002

Filed:

Nov 15, 2000

Appl. No.:

09/713581

Inventors:

Keith E. Kunz - Plano TX
James D. Huffman - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19094

US Classification:

326 81, 326 83

Abstract:

Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.

US Patent:

6480177, Nov 12, 2002

Filed:

Jun 2, 1998

Appl. No.:

09/088673

Inventors:

Donald B. Doherty - Richardson TX
Henry Chu - Plano TX
James D. Huffman - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G09G 334

US Classification:

345 84, 345 55, 345 85, 345100, 345108, 345204, 348750, 348770

Abstract:

A method of addressing an array of spatial light modulator elements. The method divides the array into blocks of elements, provides reset lines (MRST) to each of the block of elements, separate from the other blocks of elements, as well as address voltage supplies (VCC ) to each of the block of elements, separate from the other blocks of elements, addresses data to each of the blocks independent of the other blocks, resets each of the blocks, and steps address voltage to each of the block, where only blocks that are being reset receive the stepped address voltage. A spatial light modulator array ( ) is also provided that has a layout to facilitate the method, including internal or external circuitry ( ) to provide control of the stepped addressing voltages.

US Patent:

6480433, Nov 12, 2002

Filed:

Dec 1, 2000

Appl. No.:

09/727604

Inventors:

James D. Huffman - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

365201, 365207, 36523008

Abstract:

A differential amplifier circuit used to test the underlying DRAM memory cells in large area spatial light modulator (SLM) arrays by significantly increasing the cell capacitance to bitline capacitance ratio. Since for these SLM devices it is not desirable to sub-divide the DRAM array into smaller test arrays in order to reduce the bitline capacitance, this invention addresses the bitline capacitance problem by reading the differential voltage between two adjacent cells rather than the actual voltage of each cell. The approach is to load, precharge, and readout a checkerboard pattern and then repeat the process for an inverse checkerboard pattern. Cell outputs which have the same value for the two complimentary patterns indicate a cell failure. In this approach, the cell differential voltage readout is effectively doubled to approximately Â200 mVolts, providing 100% test coverage of these large area arrays. This results in an effective DRAM test procedure which is independent of bitline capacitance.

US Patent:

6483346, Nov 19, 2002

Filed:

Jan 25, 2002

Appl. No.:

10/056481

Inventors:

Keith E. Kunz - Plano TX
James D. Huffman - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19094

US Classification:

326 81, 326 83

Abstract:

Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.

US Patent:

6522454, Feb 18, 2003

Filed:

Sep 28, 2001

Appl. No.:

09/967043

Inventors:

Robert E. Meier - Dallas TX
James D. Huffman - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G02B 2600

US Classification:

359291, 359290

Abstract:

An improved DMD type spatial light modulator having an array of pixels ( ). The pixels ( ) are of the âhidden hingeâ design, each pixel having a mirror ( ) supported over a hinged yoke ( ). Addressing electrodes ( ) on an underlying metallization layer and addressing electrodes ( ) at the yoke level provide electrostatic forces that cause the mirrors to tilt and then to return to their flat state. The pixels ( ) are designed to provide increased clearance between the leading edge of the yoke ( ) and the underlying metallization layer when the mirrors ( ) are tilted. Various features of the improved pixel ( ) also improve the contrast ratio of images generated by the DMD.

US Patent:

6614262, Sep 2, 2003

Filed:

Jan 25, 2002

Appl. No.:

10/056836

Inventors:

Keith E. Kunz - Plano TX
James D. Huffman - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19094

US Classification:

326 81, 326 83

Abstract:

Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.

US Patent:

6724518, Apr 20, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/331495

Inventors:

Thomas J. Meyer - Dallas TX
Brett A. Mangrum - Dallas TX
Mark F. Reed - Richardson TX
James D. Huffman - Plano TX
Michael A. Mignardi - Richardson TX
Wei-Yan Shih - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G02B 2600

US Classification:

359291, 359290, 359224, 359646, 310 36, 347239

Abstract:

A system and method of providing a micromirror pixel that is highly resistant to bright failure states. The micromirror uses an asymmetric yoke to ensure the mirror is only attracted to the address electrode in one rotation direction. The landing mechanism on the other side of the torsion binge axis also is altered to allow the pixel to over rotate in the âoffâ direction. The over rotation ensures that light reflected by the mirror when in the off direction will miss the projection lens pupil, allowing the corresponding pixel to remain dark in both an operational and failed state.

Address:

3939 Briargrove Ln APT 2115, Dallas, TX 75287

VIN:

2G1WT58K579383852

Make:

CHEVROLET

Model:

IMPALA

Year:

2007