James D Jensen

US Patent:

6500618, Dec 31, 2002

Filed:

Oct 6, 2000

Appl. No.:

09/601412

Inventors:

Dwight L. Woolard - Raleigh NC
James O. Jensen - Bel Air MD
William R. Loerop - Aberdeen MD
David L. Rhodes - Brick NJ
Hong-Liang Cui - East Brunswick NJ
Janet L. Jensen - Bel Air MD
Alan C. Samuels - Havre de Grace MD
Thomas Koscica - Clark NJ
Harry Salem - Bel Air MD

Assignee:

Trustees of Stevens Institute of Technology - Hoboken NJ
The United States of America as represented by the Secretary of the Army - Washington DC

International Classification:

C12Q 168

US Classification:

435 6, 25033907, 25033912

Abstract:

Methods and apparatus for measuring the millimeter or submillimeter wave absorption spectra in a sample of DNA molecules are provided.

US Patent:

6662349, Dec 9, 2003

Filed:

Feb 27, 2002

Appl. No.:

10/086232

Inventors:

David A. Morgan - Fort Collins CO
Richard D. Blinne - Fort Collins CO
James A. Jensen - Eagan MN
Christopher J. Tremel - St. Louis Park MN

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

716 10, 716 8

Abstract:

A method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan for a parent macro at a parent level in a hierarchical circuit design; passing outline and pin locations from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan for the child macro at a child level in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing physical restrictions in the child macro from the child macro to the parent macro; determining a location for a cell at the parent level of the hierarchical circuit design in an area of the parent macro shared by the child macro in response to the physical restrictions passed from the child macro; passing physical constraints in the parent macro associated with placement and routing of the cell from the parent level to the child macro; and generating an abstract representation for the child macro at the child level that includes an area cut out of the child macro corresponding to the location of the cell.

US Patent:

6759979, Jul 6, 2004

Filed:

Jan 21, 2003

Appl. No.:

10/348275

Inventors:

Robert M. Vashisth - Salt Lake City UT
James U. Jensen - Salt Lake City UT
James W. Bunger - Salt Lake City UT

Assignee:

E-BusinessControls Corp. - Salt Lake City UT

International Classification:

G01S 514

US Classification:

34235713, 345419, 345629, 3482181

Abstract:

A system for capturing a virtual model of a site includes a range scanner for scanning the site to generate range data indicating distances from the range scanner to real-world objects. The system also includes a global positioning system (GPS) receiver coupled to the range scanner for acquiring GPS data for the range scanner at a scanning location. In addition, the system includes a communication interface for outputting a virtual model comprising the range data and the GPS data.

US Patent:

6796967, Sep 28, 2004

Filed:

Oct 22, 2001

Appl. No.:

10/080938

Inventors:

James U. Jensen - Salt Lake City UT

Assignee:

NPS Pharmaceuticals, Inc. - Salt Lake City UT

International Classification:

A61M 532

US Classification:

604197, 604192, 604201, 604199, 604244, 604411, 604905

Abstract:

A needle assembly for use with an injection device including a pair of housing members slidably coupled with one another. A needle is structurally attached to one of the housing members such that it is positioned within the two housing members. A first membrane is disposed on an opening of one housing member and a second membrane is disposed on an opening of the other housing member such that the needle is concealed from the view and access of a user thereof. The needle assembly may be contracted by sliding one housing member relative to the other causing the needle to penetrate one of the membranes and administer an injection into or below the skin of the user. Additionally, one or more locking mechanisms may be incorporated to prevent inadvertent needle sticks.

US Patent:

6871154, Mar 22, 2005

Filed:

Jun 11, 2003

Appl. No.:

10/459158

Inventors:

Jonathan Byrn - Kasson MN, US
James Jensen - Eagan MN, US
Roy Perrigo - Henrietta NY, US
Donald Gabrielson - Rochester MN, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F019/00

US Classification:

702117, 438 14

Abstract:

The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration (“test backplane”) for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the “test backplane”. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the “test backplane”. These pre-exiting test structures may then be connected.

US Patent:

6910201, Jun 21, 2005

Filed:

Sep 17, 2003

Appl. No.:

10/664137

Inventors:

Jonathan William Byrn - Kasson MN, US
James Arnold Jensen - Eagan MN, US
Matthew Scott Wingren - Rochester MN, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F017/50
H01L027/10

US Classification:

716 17, 257204

Abstract:

A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of the islands. The varied circuit functions include both application functions and clock functions. Interconnect layers are deposited over the substrate surface to interconnect the circuit elements within each island to complete the varied circuit functions. The varied circuit functions include varied levels of integration including at least gates, flip-flops, clock trees, and oscillators. The varied circuit functions are custom connectable to the array of unconnected transistors to form standard clock resources for the standardized silicon platform chip.

US Patent:

RE41175, Mar 30, 2010

Filed:

Jun 30, 2006

Appl. No.:

11/480248

Inventors:

Robert M. Vashisth - Salt Lake City UT, US
James U. Jensen - Salt Lake City UT, US
James W. Bunger - Salt Lake City UT, US

Assignee:

Intelisum, Inc. - Salt Lake City UT

International Classification:

G01S 5/14
G06T 15/00
G09G 5/00
H04N 5/225

US Classification:

34235713, 345419, 345629, 3482181

Abstract:

A system for capturing a virtual model of a site includes a range scanner for scanning the site to generate range data indicating distances from the range scanner to real-world objects. The system also includes a global positioning system (GPS) receiver coupled to the range scanner for acquiring GPS data for the range scanner at a scanning location. In addition, the system includes a communication interface for outputting a virtual model comprising the range data and the GPS data.

US Patent:

7800936, Sep 21, 2010

Filed:

Jul 7, 2008

Appl. No.:

12/168277

Inventors:

Michael Norris Dillon - Richfield MN, US
James Arnold Jensen - Eagan MN, US
Bret Alan Oeltjen - Elko MN, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 11/00

US Classification:

365154, 36518905, 365195

Abstract:

A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.