James L Joseph

US Patent:

55663184, Oct 15, 1996

Filed:

Aug 2, 1994

Appl. No.:

8/284384

Inventors:

James D. Joseph - Monument CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

G06F 1200

US Classification:

395445

Abstract:

A single address register control technique for a memory controller allows both cache "reads" and page-mode "writes" to be implemented without requiring separate hardware address registers for each function. Because both functions may be implemented with virtually no performance loss in a high performance memory system using a single address register, a comparator, and one additional register, the costs and other disadvantages inherent in otherwise replicating control registers are obviated.

US Patent:

58754512, Feb 23, 1999

Filed:

Mar 14, 1996

Appl. No.:

8/615392

Inventors:

James Dean Joseph - Monument CO

Assignee:

Enhanced Memory Systems, Inc. - Colorado Springs CO

International Classification:

G06F 1208

US Classification:

711105

Abstract:

A computer system with a hybrid main memory which includes both EDRAM and DRAM, with a DRAM cache provided within a designated portion of the EDRAM portion of the main memory. Read requests are handled by copying data being read from DRAM into a cache portion of EDRAM under the direction of a pseudo cache controller and decoder which converts the DRAM address to a EDRAM address corresponding to the cache location of EDRAM. Read "hit" requests are responded to by reading data directly from the cache portion of EDRAM. Write requests to DRAM are, for purposes of cache coherency when a copy of the address being written to is present in the EDRAM cache portion, accomplished by writing data both to DRAM and overwriting the stale data existing in the cache portion of EDRAM.

US Patent:

58354425, Nov 10, 1998

Filed:

Mar 22, 1996

Appl. No.:

8/620450

Inventors:

James Dean Joseph - Monument CO
Dion Nickolas Heisler - Colorado Springs CO
Doyle James Heisler - Colorado Springs CO

Assignee:

Enhanced Memory Systems, Inc. - Colorado Springs CO

International Classification:

G11C 800

US Classification:

36523008

Abstract:

An EDRAM device includes an EDRAM memory array on a semiconductor chip. A row enable signal generator and a column address latch signal generator are provided on the same semiconductor chip for generating row enable and column address latch signals for application to the EDRAM memory array.

US Patent:

59833130, Nov 9, 1999

Filed:

Apr 10, 1996

Appl. No.:

8/630489

Inventors:

Doyle James Heisler - Colorado Springs CO
James Dean Joseph - Monument CO
Dion Nickolas Heisler - Colorado Springs CO

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

G06F 1200
G06F 1206
G06F 1300

US Classification:

711105

Abstract:

The method and apparatus of the current invention relates to an intelligent cache management system for servicing a main memory and a cache. The cache resources are allocated to segments of main memory rows based on a simple or complex allocation process. The complex allocation performs a predictive function allocating scarce resources based on the probability of future use. The apparatus comprises a main memory coupled by a steering unit to a cache. The steering unit controls where in cache a given main memory row segment will be placed. The operation of the steering unit is controlled by an intelligent cache allocation unit. The unit allocates new memory access requests cache locations which are least frequently utilized. Since a given row segment may be placed anywhere in a cache row, the allocation unit performs the additional function of adjusting the column portion of a memory access request to compensate for the placement of the requested segment in the cache. The allocation unit accepts as input hit or miss information from page segment comparators greater than or equal to in number the number of segments of cache.

US Patent:

58025600, Sep 1, 1998

Filed:

Aug 30, 1995

Appl. No.:

8/521597

Inventors:

James Dean Joseph - Monument CO
Doyle James Heisler - Colorado Springs CO
Dion Nickolas Heisler - Colorado Springs CO

Assignee:

Ramton International Corporation - Colorado Springs CO

International Classification:

G06F 1200

US Classification:

711119

Abstract:

A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.

US Patent:

20150258099, Sep 17, 2015

Filed:

Mar 12, 2015

Appl. No.:

14/645578

Inventors:

- South San Francisco CA, US
James D. Joseph - San Diego CA, US
Jing Qian - San Diego CA, US
Nicholas D. Smith - San Diego CA, US
Edna Chow Maneval - San Diego CA, US
Debasish F. ROYCHOWDHURY - San Diego CA, US
Lori Friedman - San Carlos CA, US
Deepak Sampath - San Francisco CA, US

Assignee:

GENENTECH, INC. - South San Francisco CA

International Classification:

A61K 31/5375
A61K 31/4245
C12Q 1/68
A61K 31/437
A61K 31/4025
A61K 31/397
A61K 31/416
A61K 31/428

Abstract:

Described herein are methods and compositions for treating an ER-related disease condition characterized by a mutation in the ESR1 gene by administering an estrogen receptor modulator. Also described herein are methods of treating hormone resistant-estrogen receptor (ER) positive breast cancers characterized by a mutation in the ESR1 gene by administering an estrogen receptor modulator.