James Ryan Joseph

US Patent:

6718477, Apr 6, 2004

Filed:

Mar 6, 2000

Appl. No.:

09/519311

Inventors:

William C. Plants - Santa Clara CA 95051
Nikhil Mazumder - San Jose CA 94148
Arunangshu Kundu - San Jose CA 95130
James Joseph - Monument CO 80132
Wayne W. Wong - Sunnyvale CA 94086

International Classification:

G06F 108

US Classification:

713500

Abstract:

A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

US Patent:

6976185, Dec 13, 2005

Filed:

Nov 25, 2003

Appl. No.:

10/722636

Inventors:

William C. Plants - Campbell CA, US
Nikhil Mazumder - San Jose CA, US
Arunangshu Kundu - San Jose CA, US
James Joseph - Monument CO, US
Wayne W. Wong - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G06F001/08

US Classification:

713500

Abstract:

A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

US Patent:

7171575, Jan 30, 2007

Filed:

Jul 25, 2005

Appl. No.:

11/189199

Inventors:

William C. Plants - Campbell CA, US
Nikhil Mazumder - San Jose CA, US
Arunangshu Kundu - San Jose CA, US
James Joseph - Monument CO, US
Wayne W. Wong - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G06F 1/08

US Classification:

713500

Abstract:

A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

US Patent:

7484113, Jan 27, 2009

Filed:

Nov 20, 2006

Appl. No.:

11/561695

Inventors:

William C. Plants - Campbell CA, US
Nikhil Mazumder - San Jose CA, US
Arunangshu Kundu - San Jose CA, US
James Joseph - Monument CO, US
Wayne W. Wong - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G06F 1/08

US Classification:

713500

Abstract:

A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

US Patent:

7941685, May 10, 2011

Filed:

Dec 17, 2008

Appl. No.:

12/337201

Inventors:

William C. Plants - Campbell CA, US
Nikhil Mazumder - San Jose CA, US
Arunangshu Kundu - San Jose CA, US
James Joseph - Monument CO, US
Wayne W. Wong - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G06F 1/08

US Classification:

713500, 327105

Abstract:

A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

US Patent:

60494875, Apr 11, 2000

Filed:

Mar 16, 1998

Appl. No.:

9/039891

Inventors:

William C. Plants - Santa Clara CA
James Dean Joseph - Monument CO
Antony G. Bell - Los Gatos CA

Assignee:

Actel Corporation - Sunnyvale CA

International Classification:

G11C 1604
G11C 800

US Classification:

36518904

Abstract:

A dual ported (simultaneous read/write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the read port and the write port that permit the SRAM blocks to be connected into deeper and wider configurations by without any additional logic as required by the prior art. An address collision detector is provided such that when both read and write ports in the SRAM block access the same address simultaneously a choice between the data being read can be made between the data presently in the SRAM block or the new data being written to the SRAM block.