James E Keddy

US Patent:

41108230, Aug 29, 1978

Filed:

Feb 17, 1977

Appl. No.:

5/769594

Inventors:

David Cronshaw - Torrance CA
Jack E. Shemer - Los Angeles CA
William D. Turner - San Marino CA
David Hartke - Pasadena CA
James R. Keddy - Huntington Beach CA
Wilbur E. DuVall - Victorville CA
Warren M. Sterling - Hermosa Beach CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G06F 1520
G06F 314
G06F 1300

US Classification:

364200

Abstract:

A distributed function processing system utilizing a conventional microprocessor operated as a text processor in combination with a plurality of other autonomous processing devices arranged to operate in a coherent processing system. One of the autonomous processors which is a memory control processor serves to periodically overlay a random access accelerator memory with the contents of a main memory system and concurrently resolves conflicts among various other autonomous memory service requests. This processor, therefore, accommodates the data rates of the main memory. The other processor is a display processor which generates signals to a video display system to provide a visual interface to the user and is therefore tied to the video rate. Accordingly, the processing burden is distributed within processors entailing differing rates operating autonomously. The memory control processor resolves and accommodates all of the memory service requests in the system and also performs control operations to support high speed I/O devices.

US Patent:

41268946, Nov 21, 1978

Filed:

Feb 17, 1977

Appl. No.:

5/769612

Inventors:

David Cronshaw - Torrance CA
James R. Keddy - Huntington Beach CA
Jack E. Shemer - Los Angeles CA
William D. Turner - San Marino CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G06F 1308
G06F 910

US Classification:

364200

Abstract:

A mapping arrangement for memory overlay wherein the address coordinates are referenced to a main serial memory. This main memory is partitioned into pages of equal size. An accelerator memory is concurrently loaded with a few pages representing a small portion of the main memory contents and is periodically overlayed with new memory contents on a page-at-a-time basis as the using system demands. During this overlay the fields of the accelerator memory are inscribed at corresponding main memory address coordinates together with code bits indicating whether certain memory fields go together and are therefore promoted as a single unit. The resulting effect is to cause an apparent increase in page size since more than one page is promoted as a consequence of a reference to a page not contained in the accelerator memory.