James H Lin

US Patent:

6454996, Sep 24, 2002

Filed:

Feb 24, 1999

Appl. No.:

09/257429

Inventors:

James C. Lin - Orinda CA
Hidemasa Toyoshima - Shizuoka, JP

Assignee:

Lin Cubing Inc. - Orinda CA

International Classification:

A61L 207

US Classification:

422 26, 422 22, 422 23, 19 66 R, 426242

Abstract:

A method for treating agricultural products for insects, microorganisms, and other infestations is disclosed. An aspect of the method entails reducing or increasing the air pressure associated with the agricultural product, then introducing one or more treatments to the agricultural product. One treatment may comprise heat, and the heat may be in the form of steam or heated air. A second treatment may comprise electromagnetic radiation, in the form of microwave energy or high frequency waves.

US Patent:

6785685, Aug 31, 2004

Filed:

Aug 22, 2001

Appl. No.:

09/935251

Inventors:

Basuki Soetarman - Los Gatos CA
Robert Summers - San Jose CA
Subodh Monica - Gaithersburg MD
Larry An - Great Falls VA
James Lin - Cupertino CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1730

US Classification:

707101, 707 2, 707 6, 707 10, 707103

Abstract:

A method and system for transforming XML documents to and from data objects in an object oriented framework includes: importing the XML document; parsing the XML document; building a DOM tree from the parsed XML document; constructing at least one DDO or at least one XDO based on the DOM tree; and storing the DDO or XDO in a datastore. The present invention provides a transformation bridge connecting the XML world and the object world, allowing conversions from XML documents to data objects and vice versa to be performed seamlessly. It enhances the existing framework with a feature to process XML documents utilizing the existing framework facilities. Application developers can thus exploit the key advantages of XML representation as well as object orientation.

US Patent:

6859378, Feb 22, 2005

Filed:

Jun 16, 2004

Appl. No.:

10/869387

Inventors:

James K. Lin - Cupertino CA, US

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

G11C015/00

US Classification:

365 49, 36518911

Abstract:

Content addressable memory (CAM) devices according to embodiments of the present invention include high performance multiple match detection circuits therein. These match detection circuits use 2-to-1 multiple match gates that are small, consume no static power and are hierarchically cascadable. The match detection circuits are also configured so that match signal inputs see small fanouts and high speed operation can be achieved. At each intermediate and final stage of the match detection circuit, the multiple match gates process two pairs of inputs into a single pair of outputs. In particular, a match detection circuit is configured to generate a final multiple match flag (MMF) and a final any match flag (AMF) in response to input match signals, with the match detection circuit including logN stages of 2-to-1 multiple match gates, where N=2and k is a positive integer. The final MMF is set to an active level whenever at least two of the input match signals indicate a match condition and the AMF is set to an active level whenever at least one of the input match signals indicates a match condition.

US Patent:

6924994, Aug 2, 2005

Filed:

Mar 10, 2003

Appl. No.:

10/385155

Inventors:

James K. Lin - Cupertino CA, US

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

G11C015/00

US Classification:

365 49, 36518907

Abstract:

Content addressable memory (CAM) devices according to embodiments of the present invention include high performance multiple match detection circuits therein. These match detection circuits use 2-to-1 multiple match gates that are small, consume no static power and are hierarchically cascadable. The match detection circuits are also configured so that match signal inputs see small fanouts and high speed operation can be achieved. At each intermediate and final stage of the match detection circuit, the multiple match gates process two pairs of inputs into a single pair of outputs. In particular, a match detection circuit is configured to generate a final multiple match flag (MMF) and a final any match flag (AMF) in response to input match signals, with the match detection circuit including logN stages of 2-to-1 multiple match gates, where N=2and k is a positive integer. The final MMF is set to an active level whenever at least two of the input match signals indicate a match condition and the AMF is set to an active level whenever at least one of the input match signals indicates a match condition.

US Patent:

6947948, Sep 20, 2005

Filed:

Apr 23, 2002

Appl. No.:

10/128428

Inventors:

Andy I-Shin Wang - Palo Alto CA, US
David M. Choy - Los Altos CA, US
Lily L. Liang - San Jose CA, US
James J. Lin - Cupertino CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/30

US Classification:

707102

Abstract:

A relational database is disclosed which includes a number of target tables each exhibiting a different type, such as a general contact table, a personal contact table and a department contact table. The relational database includes a super-column which is divided into a number of columns corresponding to the number of types of target tables. A respective column is allocated in the super-column for each of the types of the target tables. Valuable system memory space is consequently conserved. Multiple-typed tables and multi-targeted tables are supported, and multi-version data storage capabilities are provided.

US Patent:

7082455, Jul 25, 2006

Filed:

Apr 23, 2002

Appl. No.:

10/128260

Inventors:

Tawei Hu - San Jose CA, US
James J. Lin - Cupertino CA, US
Kenneth C. Nelson - Hollister CA, US
Alan T. Yaung - San Jose CA, US
Randy Richardt - San Jose CA, US
Lily L. Liang - San Jose CA, US
Ed Gallagher - San Jose CA, US
Dwayne L. Richardson - San Francisco CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16
G06F 13/00

US Classification:

709203, 709219

Abstract:

A content management system is provided including a server computer and a client computer. The server includes a data repository and a stored procedure. The disclosed methodology provides a way of handling parameter passing of structured data for stored procedures in the system. The system is capable of both encoding data into a structured data format and decoding data from the structured data format. The structured data format employs a binary large object (BLOB) and character large object (CLOB) to achieve handling of fixed length binary data and variable length character data. Advantageously, the stored procedure interface need not be rewritten and customized for each stored procedure in the server.

US Patent:

7109760, Sep 19, 2006

Filed:

Jun 30, 2004

Appl. No.:

10/880804

Inventors:

James K. Lin - Cupertino CA, US

Assignee:

Integrated Device Technology, Inc.

International Classification:

G01R 25/00
H03D 13/00

US Classification:

327 12, 327 3, 327 7

Abstract:

Delay-locked loop (DLL) integrated circuits include digital phase comparators that are unaffected by variable duty cycle ratios. These phase comparators determine a shortest direction to phase lock before establishing a value of a compare signal (COMP) that specifies the shortest direction. The phase comparator is responsive to a reference clock signal REF and a feedback clock signal FB. These clock signals have equivalent periods and may have equivalent non-unity duty cycle ratios. The phase comparator is configured to determine whether a first degree to which the reference clock signal REF leads the feedback clock signal FB is smaller or larger than a second degree to which the reference clock signal REF lags the feedback clock signal FB. Based on this determination, the phase comparator generates a compare signal COMP that identifies a direction in time the feedback clock signal FB should be shifted to bring it into alignment with the reference clock signal REF. This direction represents a speed-up direction when the first degree is determined to be less than the second degree or a slow-down direction when the second degree is determined to be less than the first degree.

US Patent:

7119591, Oct 10, 2006

Filed:

Jul 15, 2004

Appl. No.:

10/891919

Inventors:

James K. Lin - Cupertino CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

G01R 15/12

US Classification:

327158, 327161, 327149

Abstract:

Delay-locked loop integrated circuits include a delay chain having a plurality of delay chain units. The delay chain may be a binary-weighted delay chain and the delay chain units may be arranged in ascending or descending order (e. g. , x1, x2, x4, x8,. . . ) according to delay. Each of the plurality of delay chain units may include a respective phase comparator. Each phase comparator is configured to identify whether a delay provided by the corresponding delay chain unit exceeds a fraction of a period of a reference clock signal applied to an input of the delay chain. This fraction of a period may be equivalent to one-half or other percentage of a period of the reference clock signal. The phase comparators with the delay chain units operate to generate a multi-bit delay value signal, which is provided to a delay chain control circuit.