James Lloyd

US Patent:

7102232, Sep 5, 2006

Filed:

Apr 19, 2004

Appl. No.:

10/827693

Inventors:

Lawrence A. Clevenger - LaGrangeville NY, US
Stefanie R. Chiras - Peekskill NY, US
Timothy Dalton - Ridgefield CT, US
James J. Demarest - Fishkill NY, US
Derren N. Dunn - Fishkill NY, US
Chester T. Dziobkowski - Hopewell Junction NY, US
Philip L. Flaitz - Newburgh NY, US
Michael W. Lane - Cortlandt Manor NY, US
James R. Lloyd - Katonah NY, US
Darryl D. Restaino - Modena NY, US
Thomas M. Shaw - Peekskill NY, US
Yun-Yu Wang - Poughquag NY, US
Chih-Chao Yang - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/52

US Classification:

257751, 257758, 257753, 257E2316, 257E21584

Abstract:

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

US Patent:

7402532, Jul 22, 2008

Filed:

Aug 4, 2006

Appl. No.:

11/499220

Inventors:

Lawrence A. Clevenger - LaGrangeville NY, US
Stefanie R. Chiras - Peekskill NY, US
Timothy Dalton - Ridgefield CT, US
James J. Demarest - Fishkill NY, US
Derren N. Dunn - Fishkill NY, US
Chester T. Dziobkowski - Hopewell Junction NY, US
Philip L. Flaitz - Newburgh NY, US
Michael W. Lane - Cortlandt Manor NY, US
James R. Lloyd - Katonah NY, US
Darryl D. Restaino - Modena NY, US
Thomas M. Shaw - Peekskill NY, US
Yun-Yu Wang - Poughquag NY, US
Chih-Chao Yang - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48

US Classification:

438783, 257E21576

Abstract:

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

US Patent:

7820559, Oct 26, 2010

Filed:

Jun 23, 2008

Appl. No.:

12/143917

Inventors:

Lawrence A. Clevenger - LaGrangeville NY, US
Stefanie R. Chiras - Peekskill NY, US
Timothy Dalton - Ridgefield CT, US
James J. Demarest - Fishkill NY, US
Darren N. Dunn - Fishkill NY, US
Chester T. Dziobkowski - Hopewell Junction NY, US
Philip L. Flaitz - Newburgh NY, US
Michael W. Lane - Cortlandt Manor NY, US
James R. Lloyd - Katonah NY, US
Darryl D. Restaino - Modena NY, US
Thomas M. Shaw - Peekskill NY, US
Yun-Yu Wang - Poughquag NY, US
Chih-Chao Yang - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/31
H01L 21/4763

US Classification:

438783, 438654, 257E21576

Abstract:

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

US Patent:

44007159, Aug 23, 1983

Filed:

Nov 19, 1980

Appl. No.:

6/208442

Inventors:

Steven G. Barbee - Dover Plains NY
James M. Leas - Washington DC
James R. Lloyd - Fishkill NY
Arunachala Nagarajan - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2712

US Classification:

357 49

Abstract:

A process for the preparation of a semiconductor device in a thin film of a monocrystalline semiconductor material supported on the surface of a substrate. In the process a thin film of a monocrystalline semiconductor material is formed on a substrate. The film of monocrystalline semiconductor material is doped at various depths with various types and concentrations of dopants. Thereafter, contacts are established at various depths of the doped thin film. In one embodiment, a thin film of a non-monocrystalline semiconductor material is deposited on a substrate. The thin film of non-monocrystalline semiconductor material is doped in situ as it is being deposited with various doping impurities to provide various types and concentrations of doping impurities at various depths. The thin film of non-monocrystalline semiconductor material has at least one tapered region terminating in a point. The thin film of non-monocrystalline semiconductor material is traversed with a particle beam.

US Patent:

49622943, Oct 9, 1990

Filed:

Mar 14, 1989

Appl. No.:

7/322955

Inventors:

Keith F. Beckham - Wallkill NY
David C. Challener - Hopewell Junction NY
Arunava Gupta - Valley Cottage NY
Joseph M. Harvilchuck - Billings NY
James M. Leas - Bethesda MD
James R. Lloyd - Natick MA
David C. Long - Wappingers Falls NY
Horatio Quinones - Wappingers Falls NY
Krishna Seshan - Beacon NY
Morris Shatzkes - Monsey NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B23K 2600

US Classification:

21912168

Abstract:

A method for causing an open circuit in an electrical conductor is provided, including the steps of: conducting a direct current through the conductor; and applying heat at a selected location on the conductor whereat it is desired to cause the open circuit of the conductor.

US Patent:

46222057, Nov 11, 1986

Filed:

Apr 12, 1985

Appl. No.:

6/722631

Inventors:

David P. Fouts - Stanfordville NY
Devandra Gupta - Ossining NY
Paul S. Ho - Chappaqua NY
Jasvir S. Jaspal - Poughkeepsie NY
James R. Lloyd - Fishkill NY
James M. Oberschmidt - Poughkeepsie NY
Kris V. Srikrishnan - Wappingers Falls NY
Michael J. Sullivan - Red Hook NY

Assignee:

IBM Corporation - Armonk NY

International Classification:

C22C 1106

US Classification:

420566

Abstract:

Electromigration activity is decreased and lifetime is extended in solder stripes employed as conductors and terminals on microelectronic devices by forming an alloy of a solute element, such as copper, with tin in a lead/tin solder and providing a substantially uniform distribution of particles of the intermetallic compound in the solder. The concentration of the solute element is maintained at less than about three times the tin concentration and less than about 10% of the amount of the solder.

US Patent:

20220285276, Sep 8, 2022

Filed:

Aug 3, 2020

Appl. No.:

17/632487

Inventors:

- Albany NY, US
James Lloyd - Katonah NY, US
Niaz Mahmud - Albany NY, US

International Classification:

H01L 23/532
H01L 23/522

Abstract:

Semiconducting devices, and more specifically back end of line (BEOL) portions for semiconducting devices that may include dielectric materials incorporating deuterium are disclosed. The semiconducting devices may include a back end of line (BEOL) portion electrically coupled to a front end of line (FEOL) portion. The BEOL portion may include at least one BEOL level having a dielectric layer. The dielectric layer may include at least one section formed from a low-k material including deuterium (D). The BEOL level(s) may also include an etch stop layer disposed over the dielectric layer, and at least one conductive structure disposed within the dielectric layer. The at least one conductive structure may extend through the dielectric layer and the etch stop layer, respectively.