James A Mattson

US Patent:

6658486, Dec 2, 2003

Filed:

Feb 25, 1998

Appl. No.:

09/030500

Inventors:

William B. Buzbee - Half Moon Bay CA
James S. Mattson - Campbell CA
Lacky V. Shah - Sunnyvale CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 946

US Classification:

709318

Abstract:

A blocking system intercepts communications between a software program and an operating system in order to handle blocking and unblocking of event signals. The blocking system intercepts system calls to the operating system requesting the blocking and unblocking of event signals and keeps track of which event signals are blocked and unblocked without delivering the system calls to the operating system. The blocking system also intercepts event signals from the operating system and only allows unblocked event signals to pass to the software program. Blocked event signals received by the blocking system are discarded until the program unblocks the blocked event signals. After unblocking an event signal, the blocking system determines whether a corresponding event signal was previously received and blocked. If so, the blocking system transmits a signal indicating that the event corresponding to the event signal occurred.

US Patent:

7386861, Jun 10, 2008

Filed:

Jul 23, 2003

Appl. No.:

10/625790

Inventors:

William B. Buzbee - Half Moon Bay CA, US
James S. Mattson - Campbell CA, US
Lacky V. Shah - Sunnyvale CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 9/54
G06F 9/445

US Classification:

719318, 717158, 717145, 717146, 717156

Abstract:

A blocking system intercepts communications between a software program and an operating system in order to handle blocking and unblocking of event signals. The blocking system intercepts system calls to the operating system requesting the blocking and unblocking of event signals and keeps track of which event signals are blocked and unblocked without delivering the system calls to the operating system. The blocking system also intercepts event signals from the operating system and only allows unblocked event signals to pass to the software program. Blocked event signals received by the blocking system are discarded until the program unblocks the blocked event signals. After unblocking an event signal, the blocking system determines whether a corresponding event signal was previously received and blocked. If so, the blocking system transmits a signal indicating that the event corresponding to the event signal occurred.

US Patent:

60525304, Apr 18, 2000

Filed:

Feb 25, 1998

Appl. No.:

9/030734

Inventors:

William B. Buzbee - Half Moon Bay CA
James S. Mattson - Campbell CA
Lacky V. Shah - Sunnyvale CA
David A. Dunn - San Jose CA

Assignee:

Hewlett-Packard Co. - Palo Alto CA

International Classification:

G06F 9445

US Classification:

395709

Abstract:

A dynamic translation system is configured to translate existing code into translated code which is compatible with a particular computer system. As the dynamic translation system translates the existing code, the computer system executes the translated code. Once a synchronous fault occurs, the dynamic translation system retranslates the block of code containing the synchronous fault and saves the instruction and state mappings for each instruction capable of causing the synchronous fault. Once the instruction causing the synchronous fault is reached during the retranslation process, the dynamic translation system combines the saved instruction and state mappings of the instruction causing the synchronous error with the current machine state of the computer system to form a simulated machine state. This simulated machine state represents the machine state that would have existed at the time of the synchronous fault if the original code were executing, instead of the translated code. Through techniques known in the art, the computer system utilizes the simulated machine state in order to appropriately process the synchronous fault.

US Patent:

62055453, Mar 20, 2001

Filed:

Apr 30, 1998

Appl. No.:

9/070585

Inventors:

Lacky V. Shah - Fremont CA
James S. Mattson - Campbell CA
William B. Buzbee - Half Moon Bay CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 932

US Classification:

712237

Abstract:

A run-time optimization strategy uses a trace picker to identify traces of program code in a native code pool, and a translator to translate the traces into a code cache where the traces are executed natively. Static branch prediction hints are encoded in branch instruction in the translated traces. A program module implementing the present invention is initialized with an empty code cache and a pool of instruction in a native code pool. The trace picker analyzes the instructions in the native code pool and identifies traces of instructions that tend to be executed as a group. When a trace is identified, basic blocks lying along the trace path are translated into a code cache, with static branch predictions encoded into the branch instructions of the basic blocks based on branching behavior observed when the trace is identified. Control then passes to the basic blocks in the code cache, and the basic blocks in the code cache are executed natively using the static branch prediction hints encoded into the branch instructions.

US Patent:

59336226, Aug 3, 1999

Filed:

Nov 8, 1997

Appl. No.:

8/967392

Inventors:

William B. Buzbee - Half Moon Bay CA
James S. Mattson - Campbell CA
Lacky Vasant Shah - Sunnyvale CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 9455

US Classification:

395500

Abstract:

A method for operating a computer to allow the running of a source program written for a first computer on a second computer. The second computer is assumed to include a branch taken trap. The method defines a plurality of collection points in the source program. A trap handling routine is supplied for processing traps. The trap handling routine determines whether execution has halted because of a branch taken trap at one of the collection points, and if so, retrieves information identifying an event from a queue and transferring the information and control to a handler in the source code. If execution has halted because of a branch taken trap at a location other than one of the collection points, execution of the source program is resumed with the branch taken trap armed. If execution has halted because of an asynchronous event, information specifying the event is stored in the queue, the branch taken trap is armed, and execution of the source program is resumed at the point at which execution was halted. The method may also be applied to optimizing compilers to provide a method for handling asynchronous interrupts in the optimized code.

US Patent:

20170300430, Oct 19, 2017

Filed:

Feb 28, 2017

Appl. No.:

15/444350

Inventors:

- Palo Alto CA, US
WEI XU - Palo Alto CA, US
RADU RUGINA - Palo Alto CA, US
JEFFREY W. SHELDON - Palo Alto CA, US
JAMES S. MATTSON - Seattle WA, US
RAKESH AGARWAL - Palo Alto CA, US
DAVID DUNN - Bellevue WA, US

International Classification:

G06F 12/14
G06F 9/455
G06F 9/46
G06F 21/74
G06F 9/455
G06F 9/455

Abstract:

Mechanisms to protect the integrity of memory of a virtual machine are provided. The mechanisms involve utilizing certain capabilities of the hypervisor underlying the virtual machine to monitor writes to memory pages of the virtual machine. A guest integrity driver communicates with the hypervisor to request such functionality. Additional protections are provided for protecting the guest integrity driver and associated data, as well as for preventing use of these mechanisms by malicious software. These additional protections include an elevated execution mode, termed “integrity mode,” which can only be entered from a specified entry point, as well as protections on the memory pages that store the guest integrity driver and associated data.