James Ricks Mattson

US Patent:

61122807, Aug 29, 2000

Filed:

Jan 6, 1998

Appl. No.:

9/003568

Inventors:

Lacky V. Shah - Sunnyvale CA
James S. Mattson - Campbell CA
William B. Buzbee - Half Moon Bay CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 942

US Classification:

711129

Abstract:

There is disclosed a dynamic cache which is divided into sections, or chunks, for the storage of optimized code. The optimized code may contain pointers to code in other chunks. When a cache chunk is to be reused, then the pointers to other caches, as well as the pointers from other caches to code contained with the cache that is to be removed, are changed to point to either code contained in a victim chunk of the cache, or, alternatively, to point back to the translator. The system can dynamically change the number and size of the cache chunks and the number and size of the victim chunks, if any.

US Patent:

62055453, Mar 20, 2001

Filed:

Apr 30, 1998

Appl. No.:

9/070585

Inventors:

Lacky V. Shah - Fremont CA
James S. Mattson - Campbell CA
William B. Buzbee - Half Moon Bay CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 932

US Classification:

712237

Abstract:

A run-time optimization strategy uses a trace picker to identify traces of program code in a native code pool, and a translator to translate the traces into a code cache where the traces are executed natively. Static branch prediction hints are encoded in branch instruction in the translated traces. A program module implementing the present invention is initialized with an empty code cache and a pool of instruction in a native code pool. The trace picker analyzes the instructions in the native code pool and identifies traces of instructions that tend to be executed as a group. When a trace is identified, basic blocks lying along the trace path are translated into a code cache, with static branch predictions encoded into the branch instructions of the basic blocks based on branching behavior observed when the trace is identified. Control then passes to the basic blocks in the code cache, and the basic blocks in the code cache are executed natively using the static branch prediction hints encoded into the branch instructions.

US Patent:

62233394, Apr 24, 2001

Filed:

Sep 8, 1998

Appl. No.:

9/149853

Inventors:

Lacky V. Shah - Sunnyvale CA
James S. Mattson - Campbell CA
William B. Buzbee - Half Moon Bay CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 100

US Classification:

717 5

Abstract:

The present invention is a system, method, and product for improving the speed of dynamic translation systems by efficiently positioning translated instructions in a computer memory unit. More specifically, the speed of execution of translated instructions, which is a factor of particular relevance to dynamic optimization systems, may be adversely affected by inefficient jumping between traces of translated instructions. The present invention efficiently positions the traces with respect to each other and with respect to "trampoline" instructions that redirect control flow from the traces. For example, trampoline instructions may redirect control flow to an instruction emulator if the target instruction has not been translated, or to the translation of a target instruction that has been translated. When a target instruction has been translated, a backpatcher of the invention may directly backpatch the jump to the target so that the trampoline instructions are no longer needed. A method of the present invention includes: (1) designating "chunks" of memory locations, and (2) positioning a translated trace and its corresponding trampoline instructions in the same chunk.

US Patent:

61484377, Nov 14, 2000

Filed:

May 4, 1998

Appl. No.:

9/073197

Inventors:

Lacky V. Shah - Sunnyvale CA
James S. Mattson - Campbell CA
William B. Buzbee - Half Moon Bay CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 945

US Classification:

717 4

Abstract:

A computer-implemented system and method are provided to designate traces of original instructions of an executable file at run time based on evaluations of control flow through jump instructions. Such designation typically increases the opportunities for dynamic optimization based on loop unrolling and other modifications of the control-flow structure of the executable file. The target of a jump instruction is designated as the start of a trace if the number of times that control has passed to it through any one or more jump instructions of a predetermined type of jump instruction reaches a predetermined start-trace threshold. The trace is ended if the number of times that control has passed through jump instructions of one of a variety of particular types of jump instructions reaches an end-trace threshold that is predetermined for each such type of jump instruction. The invention includes an instruction emulator, a start-end designator, a trace translator and optimizer, and a backpatch manager. The instruction emulator emulates original instructions that have not been translated.

US Patent:

20170300430, Oct 19, 2017

Filed:

Feb 28, 2017

Appl. No.:

15/444350

Inventors:

- Palo Alto CA, US
WEI XU - Palo Alto CA, US
RADU RUGINA - Palo Alto CA, US
JEFFREY W. SHELDON - Palo Alto CA, US
JAMES S. MATTSON - Seattle WA, US
RAKESH AGARWAL - Palo Alto CA, US
DAVID DUNN - Bellevue WA, US

International Classification:

G06F 12/14
G06F 9/455
G06F 9/46
G06F 21/74
G06F 9/455
G06F 9/455

Abstract:

Mechanisms to protect the integrity of memory of a virtual machine are provided. The mechanisms involve utilizing certain capabilities of the hypervisor underlying the virtual machine to monitor writes to memory pages of the virtual machine. A guest integrity driver communicates with the hypervisor to request such functionality. Additional protections are provided for protecting the guest integrity driver and associated data, as well as for preventing use of these mechanisms by malicious software. These additional protections include an elevated execution mode, termed “integrity mode,” which can only be entered from a specified entry point, as well as protections on the memory pages that store the guest integrity driver and associated data.