James Daniel Meyer

US Patent:

6356953, Mar 12, 2002

Filed:

Jun 6, 2000

Appl. No.:

09/588740

Inventors:

James W. Meyer - Shoreview MN
Paul A. Laberge - Coon Rapids MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1300

US Classification:

709253, 710101, 710128, 370402

Abstract:

A system for communicating information between requester and target devices in a computer having a multiple bus architecture. The system supports deferred transactions of cache line read requests over a host bus, e. g. , the Pentium II or Pentium Pro (P ) bus. The system employs a host bridge to issue deferred transactions over the P bus without interrupting or involving the main processor. The system comprises a first device, electrically connected to the requester, which receives a request from the requester. The system further comprises a second device, electrically connected to the first device, which transmits the request with a defer enable signal over the P bus. The system further comprises a third device, electrically connected to the P bus, which communicates the request having a defer enable signal to the target.

US Patent:

6378047, Apr 23, 2002

Filed:

Jul 7, 1997

Appl. No.:

08/888501

Inventors:

James W. Meyer - Shoreview MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1200

US Classification:

711135

Abstract:

A system and process for invalidating addresses within a cache memory system is described. The system and process allow a set-associative cache memory system in a computer to simultaneously analyze all sets corresponding to a particular address to determine whether the data at a particular address needs to be written back to the computers main memory. A set of flags is stored with each address in the cache memory so that the flags can be scrutinized to determine whether the data stored in that set is valid, but not modified.

US Patent:

6397299, May 28, 2002

Filed:

Feb 21, 1998

Appl. No.:

09/009911

Inventors:

James W. Meyer - Shoreview MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1208

US Classification:

711138, 711170

Abstract:

The present invention relates to a method in a computer system, for configuring a memory subsystem, comprising selecting a subset of main memory, integrating the subset of main memory within the computer system such that the subset is physically distinct from the main memory and configuring the subset of main memory as noncacheable memory.

US Patent:

6425056, Jul 23, 2002

Filed:

Oct 26, 1998

Appl. No.:

09/179236

Inventors:

James W. Meyer - Shoreview MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1200

US Classification:

711128, 711154, 713 2, 365 49

Abstract:

A method is described for controlling a cache memory that may be either a direct-mapped or two-way set-associative cache. The described method is performed by a configurable cache controller. The cache controller receives a configuration signal having first and second states, with the configuration signal of the first state configuring the cache controller to monitor and control a direct-mapped cache, and the configuration signal of the second state configuring the cache controller to monitor and control a two-way set-associative cache. The cache controller includes first and second comparators, each able to compare respective first and second cache tags to a memory address. Both of the comparators are enabled when monitoring cache hits to a two-way set-associative cache, whereas only one of the comparators is enabled when monitoring a direct-mapped cache. The cache controller also includes first and second control circuits, each receiving a hit signal produced by a respective one of the comparators. Thus, both of these control circuits may operate when the cache controller monitors and controls a two-way set-associative cache, while only one of the control circuits will be selectively enabled when the cache controller monitors and controls a direct-mapped cache.

US Patent:

6434720, Aug 13, 2002

Filed:

Feb 17, 1999

Appl. No.:

09/251954

Inventors:

James W. Meyer - Shoreview MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H04L 108

US Classification:

714820

Abstract:

A method of checking data integrity in a computer system which includes the acts of: transmitting primary data from a primary device to a primary CRC circuit; transmitting secondary data from a secondary device to a secondary CRC circuit, wherein the primary data and the secondary data are transmitted to their respective CRC circuits concurrently; generating a primary CRC value; generating a secondary CRC value, wherein the primary and secondary CRC values are generated concurrently; and comparing the primary CRC value with the secondary CRC value in order to generate a compare value.

US Patent:

6453448, Sep 17, 2002

Filed:

Jun 3, 1999

Appl. No.:

09/327278

Inventors:

James W. Meyer - Shoreview MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1750

US Classification:

716 4, 716 5, 716 18

Abstract:

A method and system for representing an electronic device having input-output ports and test circuits associated with the input-output ports includes: receiving a functional level description of the electronic device; determining a connectivity relationship between a first test circuit associated with a first input-output port and a second test circuit associated with a second input-output port; and generating a functional level representation of the determined connectivity relationship. Functional level descriptions include hardware description languages such as VHDL and VERILOG.

US Patent:

6535841, Mar 18, 2003

Filed:

Aug 25, 1999

Appl. No.:

09/383169

Inventors:

James W. Meyer - Shoreview MN

Assignee:

Micron Technology, Inc. - Nampa ID

International Classification:

G06F 1750

US Classification:

703 13, 703 21, 703 25, 714 42, 714719, 714736

Abstract:

A method for testing an IDE controller with random constraints, the method comprising: providing an IDE controller model having a primary and a secondary channel and a host interface; transmitting data patterns to a primary and a secondary device model; receiving the data patterns from the primary and secondary device models; arbitrating the transfer of the data patterns to and from the primary and secondary device models; and determining whether the data patterns returned from the primary and secondary device models match expected values.

US Patent:

6560680, May 6, 2003

Filed:

Nov 26, 2001

Appl. No.:

09/994302

Inventors:

James W. Meyer - Shoreview MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1208

US Classification:

711138, 711170

Abstract:

The present invention relates to a computer system comprising at least one requesting agent, a system controller and a memory subsystem comprising a main memory and a noncacheable subset of main memory physically distinct from the main memory.

Address:

1604 Ashbury Pl, Saint Paul, MN 55122

Phone:

6514543122

VIN:

5FNRL38229B044621

Make:

HONDA

Model:

ODYSSEY

Year:

2009