James W Noble

US Patent:

6573620, Jun 3, 2003

Filed:

Dec 31, 1997

Appl. No.:

09/001774

Inventors:

Dennis Craig - Sherwood OR
James Noble - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2500

US Classification:

307147, 307154, 307130, 713100

Abstract:

A microprocessor assembly is located on a daughterboard, which is configured to be physically and electrically coupled to a motherboard. One of the electrical terminals in an electrical connector between the daughterboard/motherboard is coupled to either a ground or a voltage supply V on the daughterboard, depending on the type of microprocessor used. The electrical connector passes either the ground or V signal to a semiconductor device on the motherboard to automatically identify the type of microprocessor on the daughterboard.

US Patent:

7240193, Jul 3, 2007

Filed:

Mar 1, 2002

Appl. No.:

10/085130

Inventors:

Emil J. Hatfalvi - Ellicott City MD, US
James G. Noble - Springfield VA, US

Assignee:

INVICTA Networks, Inc. - Vienna VA

International Classification:

H04L 9/00

US Classification:

713154, 713153

Abstract:

A user who is connected to an unprotected network via a protected network is able to browse the Internet without concern that unauthorized code will execute within their local workstation as the result of a vulnerability within the browser executing on a special virtual machine or a browser module. Any unauthorized code will only affect one of a special virtual machine or a browser module.

US Patent:

8254793, Aug 28, 2012

Filed:

May 27, 2008

Appl. No.:

12/127406

Inventors:

Gayle L. Noble - Boulder Creek CA, US
Lucy G. Hosking - Santa Cruz CA, US
Luke Ekkizogloy - Mountain View CA, US
James L. Noble - Boulder Creek CA, US

Assignee:

Finisar Corporation - Sunnyvale CA

International Classification:

H04J 14/02

US Classification:

398213, 398 69, 398 95

Abstract:

A tunable element of a tuning module is receptive to optical data channels of a multiplexed optical data signal, each optical data channel having a different respective wavelength. The tunable element is responsive to different stimuli such that multiple passbands of the tunable element are defined, each passband corresponding to a respective stimulus and including no more than one wavelength of the optical data channels. An optical detector communicates with the tunable element and is receptive to no more than one optical data channel from the tunable element at any given time, an output of the optical detector is an electrical data signal that corresponds to the optical data channel received by the optical detector from the tunable element. A controller communicates with the tunable element and tunes the tunable element from one optical data channel to the other by causing application of a corresponding stimulus to the tunable element.

US Patent:

20070260873, Nov 8, 2007

Filed:

Jul 2, 2007

Appl. No.:

11/822161

Inventors:

Emil Hatfalvi - Ellicott City MD, US
James Noble - Springfield VA, US

International Classification:

H04L 9/00

US Classification:

713154000

Abstract:

A user who is connected to an unprotected network via a protected network is able to browse the Internet without concern that unauthorized code will execute within their local workstation as the result of a vulnerability within the browser executing on a special virtual machine or a browser module. Any unauthorized code will only affect one of a special virtual machine or a browser module.

US Patent:

60413727, Mar 21, 2000

Filed:

Dec 30, 1996

Appl. No.:

8/774515

Inventors:

Frank P. Hart - Beaverton OR
Ravi Nagaraj - Hillsboro OR
James L. Noble - Portland OR
Neil W. Songer - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1310
H03K 509

US Classification:

710 62

Abstract:

A method and apparatus for converting a signal from a first voltage level to a second voltage level before providing the signal to a processor. A circuit board includes an interface for coupling the circuit board to a peripheral subsystem via a socket. The circuit board also includes a processor that receives signals of a first voltage level, a first signal line, and a second signal line. The first signal line is coupled to the interface and provides a reference signal to the peripheral subsystem that indicates the first voltage level. The second signal line is also coupled to the interface and provides a subsystem signal back from the peripheral subsystem after the signal has been converted to the first voltage level.

US Patent:

59832975, Nov 9, 1999

Filed:

Dec 30, 1996

Appl. No.:

8/777410

Inventors:

James L. Noble - Portland OR
Frank P. Hart - Beaverton OR
Ravi Nagaraj - Hillsboro OR
Neil W. Songer - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710102

Abstract:

A method and apparatus for upgrading a computer system from one processor generation to another processor generation. The processor and its corresponding primary bridge are included together on the same circuit board. The circuit board has an interface which can be inserted into a socket of a system. The interface socket includes the memory bus and peripheral component bus from the bridge.

US Patent:

60556455, Apr 25, 2000

Filed:

Dec 30, 1996

Appl. No.:

8/777522

Inventors:

James L. Noble - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 104

US Classification:

713501

Abstract:

A method and apparatus for providing one of two clock signals to a processor based on a reference signal. An electronic component includes a processor, a first clock source configured to provide a first clock signal, an interface for receiving a second clock signal, and a reference signal line. The first clock signal is applied to the processor if a first reference signal is applied to the reference signal line, and the second clock signal is applied to the processor if a second reference signal is applied to the reference signal line.

US Patent:

57606366, Jun 2, 1998

Filed:

Jun 28, 1996

Appl. No.:

8/673452

Inventors:

James L. Noble - Portland OR
Don J. Nguyen - Portland OR
Frank P. Hart - Beaverton OR
Barnes Cooper - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 372

US Classification:

327513

Abstract:

A method and apparatus for adjusting the clock frequency and voltage supplied to an integrated circuit. First, a signal is sent to the clock, and in response, the clock lowers the clock frequency supplied to the integrated circuit. The clock sends a signal to the voltage regulator whereupon the voltage regulator reduces the voltage supplied to the integrated circuit.