James C Norris

US Patent:

6799261, Sep 28, 2004

Filed:

Jun 28, 2002

Appl. No.:

10/184582

Inventors:

Philip E. May - Palatine IL
Kent Donald Moat - Winfield IL
Silviu Chiricescu - Chicago IL
Brian Jeffrey Lucas - Barrington IL
James M. Norris - Naperville IL
Michael Allen Schuette - Wilmette IL
Ali Saidi - Cambridge MA

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1200

US Classification:

711220, 711201, 711217, 711219

Abstract:

A memory interface device ( ) providing a fractional address interface between a data processor ( ) and a memory system ( ) and a method for retrieving intermediate data values from a memory system using fractional addressing. The device includes an address generator ( ) for generating first and second memory addresses, the first memory address being less than or equal to a specified fractional address, the second memory address being greater than or equal to the fractional address. The device also includes a memory access unit ( ) coupled to the address generator ( ) for retrieving first and second data values from the memory system ( ) at the first and second memory addresses, respectively. The device also includes a data access unit ( ) for interpolating between the first and second data values and passing the interpolated value to the data processor ( ). The memory interface has application in a variety of data processing systems, including digital signal processors and streaming vector processors.

US Patent:

6850536, Feb 1, 2005

Filed:

Jun 28, 2002

Appl. No.:

10/184609

Inventors:

Philip E. May - Palatine IL, US
Kent Donald Moat - Winfield IL, US
Silviu Chiricescu - Chicago IL, US
Brian Geoffrey Lucas - Barrington IL, US
James M. Norris - Naperville IL, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04L 1250
H04L 1254
H03M 1300

US Classification:

370428, 370383, 370392, 37039571, 710 4, 714776

Abstract:

An interconnection device () with a number of links (and ), each link having a number of link input ports (), link output ports () and storage registers (). An input selection switch () is coupled to a selected link input port to receive an input data token. The storage registers () may be used to store input data tokens. A storage access switch () is coupled to the input selection switch () and to the storage registers () and may be used to select the current input data token or a token from the storage registers as an output data token. An output selection switch () receives the output data token and provides it to a selected link output port. The interconnection device may, for example, be used to connect the inputs and outputs of the processing elements of a vector processor or digital signal processor.

US Patent:

6934938, Aug 23, 2005

Filed:

Jun 28, 2002

Appl. No.:

10/184743

Inventors:

Philip E. May - Palatine IL, US
Kent Donald Moat - Winfield IL, US
Silviu Chiricescu - Chicago IL, US
Brian Geoffrey Lucas - Barrington IL, US
James M. Norris - Naperville IL, US
Michael Allen Schuette - Wilmette IL, US
Ali Saidi - Cambridge MA, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F009/44

US Classification:

717132, 717100, 717106, 717133, 717156, 712 7, 712 8, 712201, 708490

Abstract:

A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input of the data-flow graph, a computational instruction is generated for each node of the data-flow graph, and a sink instruction is generated for each output of the data-flow graph. The computational instruction for a node includes a descriptor of an operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier. The computer is directed by a program of instructions to implement a computation representable by a data-flow graph.

US Patent:

7140019, Nov 21, 2006

Filed:

Jun 28, 2002

Appl. No.:

10/184772

Inventors:

Philip E. May - Palatine IL, US
Kent Donald Moat - Winfield IL, US
Silviu Chiricescu - Chicago IL, US
Brian Geoffrey Lucas - Barrington IL, US
James M. Norris - Naperville IL, US
Michael Allen Schuette - Wilmette IL, US
Ali Saidi - Cambridge MA, US

Assignee:

Motorola, inc. - Schaumburg IL

International Classification:

G06F 9/50
G06F 9/44

US Classification:

718102, 718105, 718104

Abstract:

A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated and the nodes are scheduled for throughput by assigning an execution cycle and a functional unit to each node of the data-flow graph. The scheduling of flexible nodes is adjusted to minimize the number of interconnections required in each execution cycle. The edges of the data-flow graph are allocated to one or more of the interconnections between functional units. The scheduling method may be used, for example, to optimize the interconnection fabric design for an ASIC or as part of a compiler for a re-configurable streaming vector processor.

US Patent:

7415601, Aug 19, 2008

Filed:

Aug 29, 2003

Appl. No.:

10/652135

Inventors:

Philip E. May - Palatine IL, US
Brian G. Lucas - Barrington IL, US
Kent D. Moat - Winfield IL, US
James M. Norris - Naperville IL, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 9/30

US Classification:

712233, 712218, 712226, 711152

Abstract:

A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for receiving an input data value tagged with a data validity tag and an output for outputting an intermediate result tagged with a data validity tag. The data validity tags indicate the validity of the data. Before a loop is executed, the data validity tags are set to indicate that the associated data values are invalid. During execution of the loop body a functional unit checks the validity of input data. If all of the input data values are valid the functional operation is performed, the corresponding data validity tag set to indicate that the result is valid. If any of the input data values is invalid, the data validity tag of the result is set to indicate that the result is invalid. To eliminate the epilog, an iteration counter is associated with each sink unit of the vector processor.

US Patent:

20080168826, Jul 17, 2008

Filed:

Jan 17, 2007

Appl. No.:

11/623892

Inventors:

Ali Saidi - St. Charles IL, US
Silviu Chiricescu - Chicago IL, US
James M. Norris - Naperville IL, US
Michael A. Schuette - Wilmette IL, US

Assignee:

MOTOROLA, INC. - Schaumburg IL

International Classification:

G01M 3/04

US Classification:

73 40

Abstract:

A system includes a first gas sensor [ to detect a first concentration of a predetermined gas and to determine a first rate of change in the first concentration over a time interval. A second gas sensor [ detects a second concentration of the predetermined gas and determines a second rate of change in the second concentration over the time interval. A third gas sensor [ detects a third concentration of the predetermined gas and determines a third rate of change in the third concentration over the time interval. The first, second, and third gas sensors each have a known location. At least one processing device [ (a) determines respective distances between a gas leak location and the respective locations of the gas sensors based on the detected rates of change, and (b) calculates a location of the gas leak based on a triangulation of the first distance, the second distance, and the third distance.

US Patent:

52257886, Jul 6, 1993

Filed:

Sep 20, 1991

Appl. No.:

7/762966

Inventors:

James R. Norris - Downers Grove IL
Jau-Huei Tang - Naperville IL
Lin Chen - Naperville IL
Marion Thurnauer - Downers Grove IL

Assignee:

The United States of America as represented by the United States
Department of Energy - Washington DC

International Classification:

H05H 708

US Classification:

328235

Abstract:

An apparatus for selecting a single synchrotron pulse from the millions of pulses provided per second from a synchrotron source includes a rotating spindle located in the path of the synchrotron pulses. The spindle has multiple faces of a highly reflective surface, and having a frequency of rotation f. A shutter is spaced from the spindle by a radius r, and has an open position and a closed position. The pulses from the synchrotron are reflected off the spindle to the shutter such that the speed s of the pulses at the shutter is governed by: s=4. times. pi. times. r. times. f. such that a single pulse is selected for transmission through an open position of the shutter.