James J Paterson

US Patent:

50574477, Oct 15, 1991

Filed:

Jul 9, 1990

Appl. No.:

7/549862

Inventors:

James L. Paterson - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2170

US Classification:

437 43

Abstract:

The invention provides an integrated circuit capacitor with a silicided polysilicon electrode (which silicide has not been used as an etch stop) as a bottom plate and a metal layer as a top plate. Subsequent to the formation of a patterned polysilicon layer, a multilevel dielectric is formed, and a via is etched therethrough to a polysilicon capacitor bottom plate. Then the polysilicon bottom plate is clad with a refractory metal silicide. The capacitor dielectric is then deposited, such a dielectric preferably consisting of an oxide/nitride layered dielectric. Contacts are etched to diffusion and to polysilicon electrodes as desired, and metal is deposited and patterned to form the top electrode of the capacitor over the capacitor dielectric, and to make contact as desired to diffusion and to polysilicon. This provides an improved silicide layer in the capacitor, as compared to processes which etch through oxide down to the silicide, and thus are using the silicide as an etch stop.

US Patent:

45970602, Jun 24, 1986

Filed:

May 1, 1985

Appl. No.:

6/729439

Inventors:

Allan T. Mitchell - Garland TX
James L. Paterson - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1140

US Classification:

365185

Abstract:

Using a method according to one embodiment of the present invention, an EPROM array may be fabricated providing a dense EPROM array. First the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1 to 1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface. The silicon dioxide layer is then further etched so that the top surfaces of the floating gates are exposed.

US Patent:

48110760, Mar 7, 1989

Filed:

Dec 5, 1986

Appl. No.:

6/938653

Inventors:

Howard L. Tigelaar - Allen TX
James L. Paterson - Richardson TX
Roger A. Haken - Dallas TX
Thomas C. Holloway - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2978
H01L 2702
H01L 2348

US Classification:

357 51

Abstract:

An integrated circuit including doubled capacitors (metal/dielectric/TiN/dielectric/polysilicon). This structure is preferably made using a patterned interlevel oxide/nitride layer to split a polycide layer, i. e. at some locations the polycide layer has low sheet resistance and at other locations the polycide layer is vertically split to provide two layers (TiN and unsilicided polysilicon), which are separated by the interlevel oxide/nitride. A double contact etch is used before the first metal interconnect layer is deposited, so that the metal makes ohmic contact to underlying silicide or silicon or TiN in some locations, and in others provides insulated metal top plates over TiN/polysilicon capacitance to provide doubled capacitors.

US Patent:

46973303, Oct 6, 1987

Filed:

May 27, 1986

Appl. No.:

6/867178

Inventors:

James L. Paterson - Richardson TX
Boger A. Haken - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21425

US Classification:

437 42

Abstract:

The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.

US Patent:

RE345350, Feb 8, 1994

Filed:

Jun 22, 1990

Appl. No.:

7/541435

Inventors:

James L. Paterson - Richardson TX
Roger A. Haken - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1140

US Classification:

365185

Abstract:

The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.

US Patent:

46139567, Sep 23, 1986

Filed:

Feb 23, 1983

Appl. No.:

6/469075

Inventors:

James L. Paterson - Richardson TX
Roger A. Haken - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1140

US Classification:

365185

Abstract:

The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.

US Patent:

55717365, Nov 5, 1996

Filed:

Jun 7, 1995

Appl. No.:

8/478642

Inventors:

James L. Paterson - Richardson TX
Gregory J. Armstrong - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218247

US Classification:

437 43

Abstract:

An EPROM disclosed in this specification includes a unique floating gate memory cell which may be charged using a reduced voltage level. The memory cells are fabricated using a mask to define the buried source, drain, and field oxide regions of the memory cell. After removal of the mask, field oxide regions are formed and a floating gate is fabricated which extends beyond the boundaries of the channel region for the floating gate field effect transistor memory cell. This extended floating gate provides additional capacitive coupling between the gate/word line and the floating gate while maintaining the same capacitive coupling between the floating gate and the channel of the floating gate field effect transistor memory cell. One embodiment discloses a silicide which is applied to the buried source and drain regions. The silicide is fabricated by forming a slot through the field oxide, forming a silicide on the diffused regions, refilling the slot with an oxide, and planarizing the resulting structure.

US Patent:

50291394, Jul 2, 1991

Filed:

Jul 19, 1989

Appl. No.:

7/382607

Inventors:

James L. Paterson - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1140

US Classification:

365218

Abstract:

An EEPROM circuit having a word-erase capability is disclosed using buried bit line fabrication techniques. The word-erasable EEPROM uses minimum additional chip area and minimum fabrication process modification.