James M Payne

US Patent:

6411549, Jun 25, 2002

Filed:

Jun 21, 2000

Appl. No.:

09/602108

Inventors:

Saroj Pathak - Los Altos Hills CA
James E. Payne - Boulder Creek CA
Jagdish Pathak - Los Altos Hills CA

Assignee:

Atmel Corporation - San Jose CA

International Classification:

G11C 1606

US Classification:

3651852, 36518521, 365210

Abstract:

A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.

US Patent:

6474489, Nov 5, 2002

Filed:

Jan 2, 2001

Appl. No.:

09/753540

Inventors:

Thomas S. Payne - Union City CA 94587
James M. Payne - Rosamond CA 93560

International Classification:

B61G 1100

US Classification:

213221, 1053925, 105393

Abstract:

A train collision attenuator mounted on a leading end of a train for attenuating the force of impact between a moving train and a pedestrian or motor vehicle. The train collision attenuator includes an energy absorbing assembly and a mounting assembly. The energy absorbing assembly includes a leading surface and the energy absorbing assembly is dimensioned and configured for attenuating the force of impact between the moving train and the pedestrian located in the path of the moving train as the pedestrian impacts against the leading surface. The mounting assembly secures the energy absorbing assembly to the leading end of the train. A lifting mechanism for moving the energy absorbing assembly between a deployed position to a retracted position is also provided. A selectively-inflatable, externally-mounted airbag including an upper pedestrian cushioning portion and a lower pedestrian support portion is also provided. An energy absorbing hydraulic cylinder and a vehicle contact plate mounted on the hydraulic cylinder piston is also provided.

US Patent:

6476785, Nov 5, 2002

Filed:

Nov 8, 1999

Appl. No.:

09/436064

Inventors:

Saroj Pathak - Los Altos Hills CA
James E. Payne - Boulder Creek CA

Assignee:

Atmel Corporation - San Jose CA

International Classification:

G05B 1942

US Classification:

345 90, 345 87

Abstract:

A driver circuit for use in an array of picture elements in a liquid crystal display is capable of displaying one set of image data while receiving a second set of image data. A first select switch transistor responsive to a first select signal controls the coupling of a first image to a first storage capacitor. A second select switch transistor responsive to a second select signal controls the coupling of a second image to a second storage capacitor. The first storage capacitor may be selectively coupled to an output node by means of a first enable switch transistor responsive to a first enable signal. The second storage capacitor may be selectively coupled to the same output node by means of a second enable switch transistor responsive to a second enable signal. By proper manipulation of the switch transistors, one storage capacitor may be coupled to the output node while the other storage capacitor is isolated from the output node and receiving new image data.

US Patent:

6618289, Sep 9, 2003

Filed:

Oct 29, 2001

Appl. No.:

10/039916

Inventors:

Saroj Pathak - Los Altos Hills CA
James E. Payne - Boulder Creek CA
Harry H. Kuo - San Jose CA

Assignee:

Atmel Corporation - San Jose CA

International Classification:

G11C 1606

US Classification:

36518525, 36518518, 36518905

Abstract:

A bit/column latch comprising a pair of first and second cross-coupled CMOS inverters. Each inverter of the pair comprises an NMOS transistor and a PMOS transistor. The first CMOS inverter has the source of its NMOS transistor coupled to ground via a control transistor and has its output connected to the associated bit line. When low voltage data intended for the associated memory cell appears on the bit line, the control transistor is barely turned on to weaken the NMOS transistor of the first inverter. This makes it easier for the data on the bit line to turn on the NMOS transistor of the second inverter so as to switch the bit latch from storing a âlowâ to storing a âhighâ. In other words, the data bit from the bit line is loaded into the bit latch. After that, the control transistor is strongly turned on and therefore it becomes transparent to the latch.

US Patent:

6619491, Sep 16, 2003

Filed:

Oct 1, 2002

Appl. No.:

10/261923

Inventors:

Thomas S. Payne - Union City CA 94587
James M. Payne - Rosamond CA 93560

International Classification:

B61G 1100

US Classification:

213221, 213223, 1053925, 105394

Abstract:

A train collision attenuator mounted on a leading end of a train for attenuating the force of impact between a moving train and a pedestrian or motor vehicle. The train collision attenuator includes an energy absorbing assembly and a mounting assembly. The energy absorbing assembly includes a leading surface and the energy absorbing assembly is dimensioned and configured for attenuating the force of impact between the moving train and the pedestrian located in the path of the moving train as the pedestrian impacts against the leading surface. The mounting assembly secures the energy absorbing assembly to the leading end of the train. A lifting mechanism for moving the energy absorbing assembly between a deployed position to a retracted position is also provided. A selectively-inflatable, externally-mounted airbag including an upper pedestrian cushioning portion and a lower pedestrian support portion is also provided. An energy absorbing hydraulic cylinder and a vehicle contact plate mounted on the hydraulic cylinder piston is also provided.

US Patent:

6744291, Jun 1, 2004

Filed:

Aug 30, 2002

Appl. No.:

10/232636

Inventors:

James E. Payne - Boulder Creek CA
Harry H. Kuo - San Jose CA
Neville B. Ichhaporia - Santa Clara CA
Jami N. Wang - Campbell CA

Assignee:

Atmel Corporation - San Jose CA

International Classification:

H03L 700

US Classification:

327143, 327198

Abstract:

A power-on reset (POR) circuit comprises a transistor connected ad diodes for setting temperature time delay coupled to a power supply voltage, a transistor switch, and buffering circuits. The trip point voltage of the POR circuit depends only on one type of transistor, such as the switching transistor so that the p-to-n skew variations do not affect the trip point. The switching transistor has a resistor connected from base to ground and another resistor connected to the power supply voltage to limit current flow during transitions.

US Patent:

6809550, Oct 26, 2004

Filed:

Sep 20, 2002

Appl. No.:

10/251402

Inventors:

Saroj Pathak - Los Altos Hills CA
James E. Payne - Boulder Creek CA
Victor V. Nguyen - San Jose CA
Harry H. Kuo - San Jose CA

Assignee:

Atmel Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 45, 326 47

Abstract:

A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path with inverter, and an output logic gate. The single path is coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.

US Patent:

6814246, Nov 9, 2004

Filed:

Jun 10, 2003

Appl. No.:

10/459238

Inventors:

Thomas S. Payne - Union City CA 94587
James M. Payne - Rosamond CA 93560

International Classification:

B61G 1100

US Classification:

213221, 213223, 1053925, 105394

Abstract:

A collision attenuating system for a moving vehicle including an energy-absorbing airbag assembly dimensioned and configured for attenuating the impact between the moving vehicle and a pedestrian or an impacted vehicle located in or crossing the path of the moving vehicle as the pedestrian or impacted vehicle impacts against the airbag assembly, a mounting bracket dimensioned and configured for being affixed to the moving vehicle, an engagement bracket affixed to the airbag assembly and engagable with the mounting bracket, and a quick-release fastener for removably engaging the engagement bracket to the mounting bracket for removably mounting the airbag assembly to the moving vehicle. The airbag assembly includes an airbag and an assembly frame supporting the airbag, a speed sensor for determining the speed of the vehicle, and a pressure regulator for controlling a pressure function of the airbag responsive to the speed sensor. The airbag assembly includes an upper deflatable airbag, and a lower pedestrian support, the pedestrian support including energy-absorbing structure. A method of using the collision attenuating system is also described.