James T Powers

US Patent:

6562711, May 13, 2003

Filed:

Jun 28, 2002

Appl. No.:

10/186072

Inventors:

James Powers - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 214763

US Classification:

438622, 438629, 438634, 438672, 438675

Abstract:

The present invention discloses a method of providing a substrate, the substrate having a first metal line and a second metal line isolated horizontally by a dielectric; forming an etch stop layer over the substrate; reducing thickness of the etch stop layer over the first metal line, leaving thickness unchanged over the second metal line; forming an interlayer dielectric (ILD) over the etch stop layer; and removing the ILD over the second metal line. The present invention further discloses a structure that includes a substrate; a first metal line and a second metal line located over the substrate; a dielectric located over the substrate adjacent to the first metal line and the second metal line; an etch stop layer located over the first metal line, the second metal line, and the dielectric, the etch stop layer being thicker over the second metal line; and a via located over the thicker etch stop layer over the second metal line.

US Patent:

6642531, Nov 4, 2003

Filed:

Dec 23, 2002

Appl. No.:

10/329290

Inventors:

James M. Powers - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G21G 500

US Classification:

2504922, 2504923, 250372, 430 5, 4302701, 422 24

Abstract:

Contamination control apparatus and methods for the removal of particulate contamination on EUV mirrors and reflective masks are provided. Embodiments in accordance with the present invention involve providing a charge to the particles and moving them away from the reflective surface by electrostatic elements. An electron source and one or more electrostatic elements are positioned adjacent the reflective surface of the reflective component. The electron source is adapted to shower electrons onto the particles in an area above the reflective surface and on the reflective surface to provide a negative charge to the particles. The electrostatic elements are adapted to provide an attractive electrostatic charge to attract the negatively charged particles on and near the reflective surface.

US Patent:

6696760, Feb 24, 2004

Filed:

Dec 10, 2002

Appl. No.:

10/316531

Inventors:

James Powers - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2348

US Classification:

257758, 257760, 257774

Abstract:

The present invention discloses a method of providing a substrate, the substrate having a first metal line and a second metal line isolated horizontally by a dielectric; forming an etch stop layer over the substrate; reducing thickness of the etch stop layer over the first metal line, leaving thickness unchanged over the second metal line; forming an interlayer dielectric (ILD) over the etch stop layer; and removing the ILD over the second metal line. The present invention further discloses a structure that includes a substrate; a first metal line and a second metal line located over the substrate; a dielectric located over the substrate adjacent to the first metal line and the second metal line; an etch stop layer located over the first metal line, the second metal line, and the dielectric, the etch stop layer being thicker over the second metal line; and a via located over the thicker etch stop layer over the second metal line.

US Patent:

7029723, Apr 18, 2006

Filed:

Jan 7, 2003

Appl. No.:

10/337524

Inventors:

Robert Meagley - Beaverton OR, US
Kevin P. O'Brien - Portland OR, US
Michael D. Goodner - Hillsboro OR, US
James Powers - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

C23C 16/38
C23C 16/28

US Classification:

4272495, 42725538

Abstract:

Carborane may be used as a precursor to form low dielectric constant dielectrics. The carborane material may be modified to enable it to be deposited by chemical vapor deposition.

US Patent:

7068347, Jun 27, 2006

Filed:

Dec 20, 2002

Appl. No.:

10/327251

Inventors:

James M. Powers - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03B 27/52
G03B 27/42
G03B 27/62
G03F 1/00

US Classification:

355 30, 355 53, 355 75, 430 5

Abstract:

Pellicles separated by a distance sufficient to allow a purge gas help repair damage to at least one of the pellicles caused by exposure to an incident radiation and allowing at least a minimum amount of radiation to reach a semiconductor wafer sufficient to perform a desired photolythography process. Moreover, the two pellicles separated by a sufficient distance such that a dispersed purge gas dispersed between the pellicles will not absorb more than an amount of energy from the incident radiation so as to prevent a desired amount of the radiation to reach a semiconductor wafer located a certain distance away from the pellicles.

US Patent:

7126223, Oct 24, 2006

Filed:

Sep 30, 2002

Appl. No.:

10/261426

Inventors:

James Powers - Aloha OR, US
Kevin P. O'Brien - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/52

US Classification:

257760, 257776

Abstract:

A method is disclosed of forming an air gap using etch back of an inter layer dielectric (ILD) with self-alignment to metal pattern. The method entails forming a first metallization layer deposited on a first dielectric, forming a second metallization layer deposited on a second dielectric, wherein the second metallization layer is spaced apart from the first metallization layer, forming a sacrificial ILD between the first and second metallization layers, forming a diffusion layer over the first and second metallization layers and over the sacrificial ILD, and removing the sacrificial ILD to form an air gap between the first and second metallization layers. This method is particular applicable for dual copper damascene processes.

US Patent:

7214452, May 8, 2007

Filed:

Nov 7, 2002

Appl. No.:

10/289611

Inventors:

James M. Powers - Aloha OR, US
Robert P. Meagley - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 9/00

US Classification:

430 5, 1562722, 428 14, 428421, 428422

Abstract:

Exposure systems may use pellicles made of perfluoropoly-ether. These materials may exhibit reduced darkening upon repeated exposures compared to other materials.

US Patent:

8513111, Aug 20, 2013

Filed:

Jul 12, 2006

Appl. No.:

11/485078

Inventors:

Robert P. Meagley - Beaverton OR, US
Kevin P. O'Brien - Portland OR, US
Michael D. Goodner - Hillsboro OR, US
James Powers - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/58

US Classification:

438619, 438637

Abstract:

A semiconductor structure may be covered with a thermally decomposing film. That film may then be covered by a sealing cover. Subsequently, the thermally decomposing material may be decomposed, forming a cavity.