James J Radigan

US Patent:

6738967, May 18, 2004

Filed:

Mar 14, 2000

Appl. No.:

09/524440

Inventors:

James J. Radigan - Redmond WA

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 945

US Classification:

717146

Abstract:

A developers system compiles a source-language program by parsing it into an intermediate language (IL) program that is independent of the architecture or resources of any particular processor. This system generates a set of machine independent annotations that record attributes and structure of the IL program such as variable definitions and uses. The annotations are in the form of a unique graph structure. Further annotations are used to associate the machine specific optimization information with each of many different microprocessors. The IL program and all the annotations are distributed to multiple user systems having mutually different virtual machines that translate the IL program into object language for their respective different processors. Optimizers in the virtual machines select graph edges based on the machine specific annotations to generate an optimized object program. The translators are table-driven.

US Patent:

7389501, Jun 17, 2008

Filed:

Feb 18, 2003

Appl. No.:

10/368746

Inventors:

Karim T. Farouki - Seattle WA, US
James J. Radigan - Redmond WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 9/44

US Classification:

717152, 717154, 717158, 717159

Abstract:

The construction of Static Single Assignment form (SSA) is used as a dynamic conflict graph so that while constructing SSA in linear time, the program being analyzed is simultaneously register allocated. When allocating a register for the symbol, the conflict set is examined so that the register chosen for the symbol is not used by a symbol in the conflict set. When a symbol is register-allocated, the symbol is added to all the conflict set of all live symbols. A live symbol is determined by keeping two counters, called herein a use counter and a use threshold counter. Both counters are initialized when a definition of a symbol is encountered in a block. Both counters are incremented when a use of the symbol is encountered when traversing a block in a depth-first downward traversal. The use count is decremented when a use is detected when traversing the block in an upward traversal. A symbol is live when the use count is less than the use count threshold and the use count is greater than zero when a register is allocated.

US Patent:

7539983, May 26, 2009

Filed:

Jan 18, 2005

Appl. No.:

11/039241

Inventors:

Ian M. Bearman - Seattle WA, US
James J. Radigan - Sammamish WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 9/45

US Classification:

717146, 717154, 717155, 717157

Abstract:

A compiler that forms an intermediate representation of a program using a flow graph with less than all possible edges used to model asynchronous transfers within the program. The flow graph is formed in multiple phases. In one phase, the flow graph is formed without modeling asynchronous transfers. In later phases, representations of the effects of the asynchronous transfers are selectively added. As part of the later phases, edges modeling a possible asynchronous transfer are added to the flow graph following definitions in protected regions of variables that are live outside the protected region. A modified definition of live-ness of a variable is used to incorporate use of the variable in any region, including the protected region, following an asynchronous transfer. Edges from the protected region are also added to the model if the only use of the defined variable is in a handler.

US Patent:

7631304, Dec 8, 2009

Filed:

Jan 14, 2005

Appl. No.:

11/036862

Inventors:

Ian M. Bearman - Seattle WA, US
James J. Radigan - Sammamish WA, US

International Classification:

G06F 9/45

US Classification:

717156, 717144, 717159

Abstract:

A compiler that forms an intermediate representation of a program using a flow graph with less than all possible edges used to model asynchronous transfers within the program. The flow graph is formed in multiple phases. In one phase, the flow graph is formed without modeling asynchronous transfers. In later phases, representations of the effects of the asynchronous transfers are selectively added. As part of the later phases, edges modeling a possible asynchronous transfer are added to the flow graph following definitions in protected regions of variables that are live outside the protected region. A modified definition of live-ness of a variable is used to incorporate use of the variable in any region, including the protected region, following an asynchronous transfer. Edges from the protected region are also added to the model if the only use of the defined variable is in a handler.

US Patent:

7634778, Dec 15, 2009

Filed:

Jun 26, 2003

Appl. No.:

10/609267

Inventors:

Scott D. Mosier - Redmond WA, US
Ian H. Carmichael - Sammamish WA, US
Lawrence B. Sullivan - Renton WA, US
James J. Radigan - Redmond WA, US
David N. Cutler - Medina WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 3/00
G06F 9/44
G06F 9/46
G06F 9/45
G06F 11/00

US Classification:

719318, 717140, 717148, 717151, 717154, 714 2, 714 25

Abstract:

In an exemplary media implementation, one or more electronically-accessible media include electronically-executable instructions that utilize an application programming interface, the application programming interface facilitating creation of callback-type dynamic function tables; each callback-type dynamic function table including a begin address, an end address, and a callback function, each callback-type dynamic function table corresponding to a code heap that stores code for multiple functions in a runtime environment; wherein interaction between the runtime environment and an operating system is precipitated upon calling the callback function to acquire exception handling and/or unwind information. In another exemplary media implementation, one or more electronically-accessible media include at least part of an operating system that is configured to request from a runtime environment exception handling and/or unwinding information for functions that are managed by the runtime environment.

US Patent:

20100325608, Dec 23, 2010

Filed:

Jun 19, 2009

Appl. No.:

12/487663

Inventors:

James Radigan - Sammamish WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 9/44
G06F 9/45

US Classification:

717106, 717114, 717140, 717113, 717156

Abstract:

A generated grouped representation of existing source code can define regions of the existing source code. A set of the regions that can run in parallel can be identified based on the grouped representation. The grouped representation can be converted into a modified representation, such as modified source code or a modified intermediate compiler representation, which can be configured to be resolved or executed to self-schedule the set of regions to run in parallel as a set of tasks. Additionally, the source code can include one or more exception handling routines, and user input can be received to identify in one or more lambda expressions one or more regions of the source code to be run in parallel as one or more tasks.

US Patent:

54817366, Jan 2, 1996

Filed:

Feb 17, 1993

Appl. No.:

8/018683

Inventors:

David A. Schwartz - Moorpark CA
James J. Radigan - Sunnyvale CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

G06F 930

US Classification:

395800

Abstract:

A processing element (42) design is provided for improving performance and reducing the number (30') of memory ports by eliminating the dedication of ports to specific functional units (22, 24, 26, 28) and by providing data paths (46, 48, 50, 52) to other forward results from functional unit outputs directly to other functional unit inputs.

US Patent:

55554288, Sep 10, 1996

Filed:

Mar 10, 1995

Appl. No.:

8/402406

Inventors:

James J. Radigan - Sunnyvale CA
David A. Schwartz - Moorpark CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

G06F 1580

US Classification:

395800

Abstract:

Disclosed is a masking technique for a SIMD processor (10) which is capable of masking a plurality of individual machine operations within a single instruction incorporating a plurality of operations. To accomplish this each different machine operation within the instruction includes a number of masking bits which address a specific location in a mask register (60). The mask register (60) includes a mask bit bank (62). The mask location selected within the mask register (60) is bit-wise ANDed with a mask context bit (66) in order to establish whether the processing element will be enabled or disabled for a particular conditional sub-routine which is called. One of the bit locations in the mask bit bank (60) is a hard-wired unconditional bit which overrides the mask context bit (66) in order to enable the processing elements in special situations. In addition, a scalar mask bit is provided to facilitate scalar processing. By this operation, instructional parallelism can be incorporated in order to increase through-put of the processor.