James A Raymond

US Patent:

44059795, Sep 20, 1983

Filed:

Oct 6, 1980

Appl. No.:

6/194495

Inventors:

Thomas O. Holtey - Newton MA
Steven S. Noyes - Boylston MA
James C. Raymond - Framingham MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 304

US Classification:

364200

Abstract:

A data processing system having a communications subsystem operating in a byte control protocol mode includes apparatus for establishing byte synchronization between the data circuit terminating equipment (DCE) and the communications subsystem. The apparatus includes a flop for receiving a stream of predetermined binary bits, a counter generating count signals indicative of the number of binary bits between a byte timing signal from the DCE and the last binary ONE bit of the last byte containing all binary ONE bits, a shift register for the serial shifting of the transmitted data bits and a multiplexer responsive to the count signals for selecting the shift register terminal, thereby timing the byte timing signal to the binary bit stream of data bits, including bytes of all binary ONE bits and a byte of all binary ZERO bits, followed by bytes of data bits.

US Patent:

42610354, Apr 7, 1981

Filed:

Sep 28, 1979

Appl. No.:

6/079961

Inventors:

James C. Raymond - Framingham MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 300
G06F 1100

US Classification:

364200

Abstract:

A hardware/firmware communication line adapter for interfacing a communication processor to a broadband high level data link communication channel. Transmit and receive data and control characters received either from the processor or from a communication channel device are processed under the control of the adapter firmware to effectuate CRC checking, byte size control, extended and variable field format control, partial last byte control, and block transfer control functions on the transmitted/received data stream. First-in-first-out (FIFO) buffer memories are employed in the transmit circuits to queue a frame of transmit data and control characters at the adapter whereby the communication processor/adapter interface control is simplified. Similarly, a FIFO buffer is employed in the receive circuits to reduce the frequency of receive interrupts and to enable block transfer of received data to the processor.

US Patent:

43793401, Apr 5, 1983

Filed:

Oct 6, 1980

Appl. No.:

6/194698

Inventors:

Thomas O. Holtey - Newton MA
Richard P. Kelly - Nashua NH
Steven S. Noyes - Framingham MA
James C. Raymond - Framingham MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 304

US Classification:

364900

Abstract:

A data processing system includes a communications subsystem communicating with a number of devices. A counter monitors the communication line to detect when a communication line goes idle, that is at least 15 successive binary ONE bits appear on the line for the bit oriented protocol mode. The counter advances on successive binary ONE bits and is forced to a hexadecimal ZERO in response to a binary ZERO. If the counter reaches a count of hexadecimal F (decimal 15) a carry signal from the counter prevents the counter from advancing and initiates an idle link state.

US Patent:

44183844, Nov 29, 1983

Filed:

Oct 6, 1980

Appl. No.:

6/194655

Inventors:

Thomas O. Holtey - Newton MA
Richard P. Kelly - Nashua NH
Steven S. Noyes - Boylston MA
James C. Raymond - Framingham MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 300
G06F 1106

US Classification:

364200

Abstract:

A data processing system operating in a bit oriented protocol (BOP) mode of operation senses a transmit underrun; that is, the subsystem is not receiving data from a microprocessor fast enough to maintain the synchronous transmission over the communication line. Apparatus senses the transmit underrun state and generates an abort sequence of bits containing from 8 to 13 successive binary ONE bits.

US Patent:

42544629, Mar 3, 1981

Filed:

Jun 1, 1978

Appl. No.:

5/911635

Inventors:

James C. Raymond - Framingham MA
Richard A. Lemay - Bolton MA
Richard P. Kelly - Nashua NH

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 300

US Classification:

364200

Abstract:

A hardware/firmware control system is disclosed for accommodating the concurrent bi-directional transfer of information between a communications channel such as a telephone line and a communications processor in a data processing system.

US Patent:

42479410, Jan 27, 1981

Filed:

Jun 28, 1979

Appl. No.:

6/053109

Inventors:

James C. Raymond - Framingham MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1130

US Classification:

371 15

Abstract:

A data communication simulator system wherein the basic operational conditions of a bit and byte synchronized data network may be simulated by generation of a bit timing signal, a byte timing signal, data signals, and control and status indication signals. Manual as well as automatic testing modes are provided, the manual mode including a signal stepping control arranged to enable either full or half cycle operation.