James D Schaeffer

US Patent:

6949455, Sep 27, 2005

Filed:

Oct 1, 2003

Appl. No.:

10/677070

Inventors:

Daniel Thanh-Khac Pham - Austin TX, US
James K. Schaeffer - Austin TX, US
Melissa O. Zavala - Pflugerville TX, US
Sherry G. Straub - Pflugerville TX, US
Kimberly G. Reid - Austin TX, US
Marc Rossow - Austin TX, US
James P. Geren - Pflugerville TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L021/3205

US Classification:

438587, 438592, 438583, 438275, 438218, 438519

Abstract:

A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.

US Patent:

6987063, Jan 17, 2006

Filed:

Jun 10, 2004

Appl. No.:

10/865452

Inventors:

Olubunmi O. Adetutu - Austin TX, US
James K. Schaeffer - Austin TX, US
Dina H. Triyoso - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/44

US Classification:

438685, 438681, 438763, 438785, 438240, 438625, 438677, 438783, 438754, 171 93, 171 84, 171 89, 4272481, 427252, 42725531, 42725536, 427343

Abstract:

A metal-containing semiconductor layer having a high dielectric constant is formed with a method that avoids inclusion of contaminant elements that reduce dielectric constant of metals. The metal-containing semiconductor layer is formed overlying a substrate in a chamber. A precursor is introduced to deposit at least a portion of the metal-containing semiconductor layer. The precursor contains one or more elements that, if allowed to deposit in the metal-containing layer, would become impurity elements. A reactant gas is used to purify the metal-containing layer by removing impurity elements from the metal-containing layer which were introduced into the chamber by the precursor.

US Patent:

7015153, Mar 21, 2006

Filed:

Oct 20, 2004

Appl. No.:

10/969634

Inventors:

Dina H. Triyoso - Austin TX, US
Olubunmi O. Adetutu - Austin TX, US
David C. Gilmer - Austin TX, US
Darrell Roan - Austin TX, US
James K. Schaeffer - Austin TX, US
Philip J. Tobin - Austin TX, US
Hsing H. Tseng - Austin TX, US

Assignee:

Freescale Semiconductor, inc. - Austin TX

International Classification:

H01L 21/31

US Classification:

438785, 438778

Abstract:

A method for forming at least a portion of a semiconductor device includes providing a semiconductor substrate, flowing a first precursor gas over the substrate to form a first metal-containing layer overlying the semiconductor substrate, and after completing said step of flowing the first precursor gas, flowing a first deuterium-containing purging gas over the first metal-containing layer to incorporate deuterium into the first metal-containing layer and to also purge the first precursor gas. The method may further include flowing a second precursor gas over the first metal-containing layer to react with the first metal-containing layer to form a metal compound-containing layer, and flowing a second deuterium-containing purging gas over the metal compound-containing layer to incorporate deuterium into the metal compound-containing layer and to also purge the second precursor gas.

US Patent:

7132360, Nov 7, 2006

Filed:

Jun 10, 2004

Appl. No.:

10/865268

Inventors:

James K. Schaeffer - Austin TX, US
Darrell Roan - Austin TX, US
Dina H. Triyoso - Austin TX, US
Olubunmi O. Adetutu - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/4763
H01L 21/8344
H01L 21/8242
H01L 21/336

US Classification:

438622, 438240, 438238, 438381, 257E2129

Abstract:

A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor substrate. The one or more metals enhance nucleation for subsequent material growth. A metal-containing layer is formed on the exposed surface of the semiconductor substrate that has been treated. The treatment of the exposed surface of the semiconductor substrate assists the metal-containing layer to coalesce. In one embodiment, treatment of the exposed surface to enhance nucleation may be performed by spin-coating, atomic layer deposition (ALD), physical layer deposition (PVD), electroplating, or electroless plating. The one or more metals used to treat the exposed surface may include any rare earth or transition metal, such as, for example, hafnium, lanthanum, etc.

US Patent:

7303983, Dec 4, 2007

Filed:

Jan 13, 2006

Appl. No.:

11/331763

Inventors:

Dina H. Triyoso - Austin TX, US
Olubunmi O. Adetutu - Austin TX, US
James K. Schaeffer - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/3205

US Classification:

438592, 257E21021

Abstract:

A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer () over a gate dielectric layer (), forming a transition layer () over the first conductive layer using an atomic layer deposition process in which an amorphizing material is increasingly added as the transition layer is formed, forming a capping conductive layer () over the transition layer, and then selectively etching the capping conductive layer, transition layer, and first conductive layer, resulting in the formation of an etched gate stack (). By forming the transition layer () with an atomic layer deposition process in which the amorphizing material (such as silicon, carbon, or nitrogen) is increasingly added, the transition layer () is constructed having a lower region (e. g. , ) with a polycrystalline structure and an upper region (e. g. , ) with an amorphous structure that blocks silicon diffusion.

US Patent:

7445976, Nov 4, 2008

Filed:

May 26, 2006

Appl. No.:

11/420525

Inventors:

James K. Schaeffer - Austin TX, US
Rama I. Hegde - Austin TX, US
Srikanth B. Samavedam - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

438197, 438199, 438151

Abstract:

A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the control electrode stack is a gate stack for a MOSFET. In one example, the layer includes aluminum fluoride.

US Patent:

7648884, Jan 19, 2010

Filed:

Feb 28, 2007

Appl. No.:

11/680199

Inventors:

Byoung W. Min - Austin TX, US
James K. Schaeffer - Austin TX, US
David C. Sing - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/20

US Classification:

438385, 438659, 257E21204

Abstract:

A resistive device () and a transistor () are formed. Each uses a portion of a metal layer () that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer () overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.

US Patent:

7655550, Feb 2, 2010

Filed:

Jun 30, 2006

Appl. No.:

11/427980

Inventors:

James K. Schaeffer - Austin TX, US
David C. Gilmer - Austin TX, US
Mark V. Raymond - Austin TX, US
Philip J. Tobin - Austin TX, US
Srikanth B. Samavedam - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/4763

US Classification:

438592, 438591, 438257, 257310, 257407

Abstract:

A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.