James E Small

US Patent:

50791770, Jan 7, 1992

Filed:

Sep 19, 1989

Appl. No.:

7/409545

Inventors:

Craig S. Lage - Puyallup WA
James E. Small - Puyallup WA
Bamdad Bastani - Danville CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21265

US Classification:

437 31

Abstract:

A method of making complementary vertical bipolar transistors and complementary field effect transistors on the same substrate is described. The process includes forming buried layers in a semiconductor substrate which are spaced apart in a self-aligned manner by use of a lateral etching technique to undercut the mask used for definition of the buried layers. In the process, the collector and base contacts of the bipolar devices and the corresponding conductivity-type sources and drains of the field effect transistors are combined to minimize processing steps. The process also includes a silicided polycrystalline silicon layer used to form resistors and contact the various transistors.