James B Smart

US Patent:

7921431, Apr 5, 2011

Filed:

Jan 20, 2006

Appl. No.:

11/336032

Inventors:

James Winston Smart - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 13/00
G06F 9/46
G06F 9/44

US Classification:

719328, 711114, 718104, 719321

Abstract:

An API in an NPIV-compatible SAN is disclosed that includes functions for creating a vlink, replicating driver software for managing the vlink, monitoring resources in an HBA, or removing a target so that resources can be freed up for other vlinks. The API is part of a driver that communicates with a host OS and also communicates with an HBA to establish the vlinks between the host OS and FC devices. To create vlinks, an “add” function in the API is called by the OS. In addition, when a new vlink is created, a single version of an HBA interface function block is maintained in the driver, but a discovery function block, SCSI bus function block, and I/O function block are all duplicated, forming one logical vlink driver for each vlink. To obtain HBA resource information, a resource monitoring functions in the API may be called by the OS.

US Patent:

20110258352, Oct 20, 2011

Filed:

Apr 20, 2010

Appl. No.:

12/764002

Inventors:

James B. WILLIAMS - Costa Mesa CA, US
Shawn Adam Clayton - Costa Mesa CA, US
Maria Clara Gutierrez - Costa Mesa CA, US
Alexander Nicolson, IV - Costa Mesa CA, US
James Winston Smart - Costa Mesa CA, US
John Leland Wood - Cost Mesa CA, US
David James Duckman - Costa Mesa CA, US
Carl John Lindeborg - Costa Mesa CA, US
William Irving Leavitt - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 13/14
G06F 13/28
G06F 13/20

US Classification:

710107, 710313, 710308

Abstract:

A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

US Patent:

20220337524, Oct 20, 2022

Filed:

Apr 19, 2021

Appl. No.:

17/234223

Inventors:

- Singapore, SG
James Winston Smart - Irvine CA, US
Mark Karnowski - Irvine CA, US
Ravi Shenoy - San Jose CA, US
Gregorio Gervasio, JR. - San Jose CA, US
Lalit Chhabra - San Jose CA, US
Chakradhara Raj Yadav Aradhyula - San Jose CA, US

International Classification:

H04L 12/815

Abstract:

Systems and methods of communicating in a network use rate limiting. Rate limiting units (either receive side or transmit side) can perform rate limiting in response to a) a maximum number of bytes that can be solicited over a first period of time is exceeded, b) a maximum number of bytes that are outstanding over a second period of time is exceeded; or c) a maximum number of commands that are outstanding over a period of time is exceeded as part of CMD_RXRL. The CMD_RXRL, can have three components (a) max bytes, b) outstanding bytes, c) outstanding commands. TXRL, contains the component of max bytes or maximum number of bytes that can be transmitted over a third period of time to match the speed of a receive link, or any node or link through the network/fabric.

US Patent:

20190324926, Oct 24, 2019

Filed:

Apr 19, 2018

Appl. No.:

15/957264

Inventors:

- Singapore, SG
Mark Karnowski - Huntington Beach CA, US
James Smart - Laguna Hills CA, US
Ravi Shenoy - Sunnyvale CA, US
Lalit Chhabra - Fremont CA, US
Gregorio Gervasio, JR. - Santa Clara CA, US
Tuong Le - Irvine CA, US
Vuong Nguyen - Aliso Viejo CA, US

International Classification:

G06F 13/16
G06F 13/42

Abstract:

A system, method, and adaptor that facilitate data transmission are described. One example of the disclosed system facilitates the chip-to-chip transport of header descriptors and payloads. The system may include a source chip, a destination chip, and a set of queues describing buffer memory locations for staging header descriptors and payloads to be transferred from the source chip to the destination chip, where the set of queues are directly accessible to the source chip and to the destination chip.

US Patent:

20160110301, Apr 21, 2016

Filed:

Dec 17, 2015

Appl. No.:

14/973208

Inventors:

- Singapore, SG
Shawn Adam Clayton - Costa Mesa CA, US
Maria Clara Gutierrez - Costa Mesa CA, US
Alexander Nicolson, IV - Costa Mesa CA, US
James Winston Smart - Costa Mesa CA, US
John Leland Wood - Costa Mesa CA, US
David James Duckman - Costa Mesa CA, US
Carl John Lindeborg - Costa Mesa CA, US
William Irving Leavitt - Costa Mesa CA, US

International Classification:

G06F 13/16
G06F 13/42
G06F 13/40

Abstract:

A system for enabling input/out virtualization for a device is disclosed. In one embodiment the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.