James R Smart

US Patent:

20220334985, Oct 20, 2022

Filed:

Apr 16, 2021

Appl. No.:

17/232944

Inventors:

- Singapore, SG
Kenny Wu - San Jose CA, US
Ravi Shenoy - San Jose CA, US
Gregorio Gervasio, JR. - San Jose CA, US
Lalit Chhabra - San Jose CA, US
Mark Karnowski - Irvine CA, US
James Winston Smart - Irvine CA, US
Vuong Cao Nguyen - Irvine CA, US

International Classification:

G06F 13/16
G06F 13/28
G06F 12/1009
G06F 12/0806

Abstract:

Systems and methods relate to a bus adapter for a storage network. The bus adaptor includes a context memory comprising a first storage for uncacheable exchange resource indicators (XRI) and a second storage for cacheable XRI. The bus adapter also includes a host backing store unit configured to provide access to the different tier memories present locally or externally in the host memory extension using several caching sub-units and with the capability of an optional pinning operation for the cacheable XRI based upon at least one of input/output phase, first in line up to a limit, a region of a virtual context address associated with the cacheable XRI indicators, a protocol associated with the cacheable XRI, a size of a transaction, or work queue information.

US Patent:

20180074978, Mar 15, 2018

Filed:

Nov 21, 2017

Appl. No.:

15/819700

Inventors:

- Singapore, SG
Shawn Adam Clayton - San Jose CA, US
Maria Clara Gutierrez - San Jose CA, US
Alexander Nicolson, IV - San Jose CA, US
James Winston Smart - San Jose CA, US
John Leland Wood - San Jose CA, US
David James Duckman - San Jose CA, US
Carl John Lindeborg - San Jose CA, US
William Irving Leavitt - San Jose CA, US

International Classification:

G06F 13/16
G06F 13/42
G06F 13/40
G06F 13/38

Abstract:

A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.