James Edward Thiele

US Patent:

50974220, Mar 17, 1992

Filed:

Jun 29, 1989

Appl. No.:

7/374485

Inventors:

Ludlow V. Corbin - Seattle WA
Steven G. Danielson - Seattle WA
Richard E. Oettel - Bellevue WA
Mark E. Rossman - Redmond WA
James E. Thiele - Seattle WA

Assignee:

Cascade Design Automation Corporation - Bellevue WA

International Classification:

G06F 1560

US Classification:

364491

Abstract:

A method and apparatus for determining integrated circuit layouts from a virtual circuit description and specification of a technology. Starting with high-level descriptions of a circuit, a virtual geometric description of the circuit is developed using a virtual grid described in terms of reference points relative to a substrate surface. The relationships among the reference points are expressed as fractions of variables that can also be used to define the design rules. When the technology is specified, the relationships among the reference points is determined, as in the layout of the integrated circuit.