James F Wiley

US Patent:

6381358, Apr 30, 2002

Filed:

Apr 27, 2000

Appl. No.:

09/559512

Inventors:

Anthony Vacca - Ceder Park TX
Thomas Vavul - San Francisco CA
Donald J. Parker - San Jose CA
Zain Saidin - Sunnyvale CA
Sterling G. Watson - Palo Alto CA
James N. Wiley - Menlo Park CA

Assignee:

KLA-Tencor Corporation - San Jose CA

International Classification:

G06K 900

US Classification:

382145, 382144, 348 86

Abstract:

A method and software program for determining printability of a defect on a reticle or photomask onto a substrate during processing. That is performed by creating a pixel grid image having a plurality of individual pixel images showing the defect. A gray scale value is assigned to each pixel image of the pixel grid image and a probable center pixel of the defect is selected. Then the polarity of the defect is determined, with a coarse center pixel of the defect optionally selected using the probable center defect and polarity of the defect. If a coarse center pixel is selected, then a fine center of the defect can optionally be selected from the coarse center pixel and polarity of the defect. From the center pixel the physical extent of the defect can be determined followed by the determination the transmissivity energy level of the physical extent of the defect. Optionally, the proximity of the defect to a pattern edge on the reticle or photomask can be determined using the physical extent and polarity of the defect.

US Patent:

6516085, Feb 4, 2003

Filed:

May 3, 1999

Appl. No.:

09/304437

Inventors:

James N. Wiley - Menlo Park CA
Jun Ye - Palo Alto CA
David S. Alles - Los Altos CA
Yen-Wen Lu - Los Altos CA
Yu Cao - Sunnyvale CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G06K 900

US Classification:

382144, 348 87

Abstract:

Disclosed is a method of inspecting a reticle defining a circuit layer pattern that is used within a corresponding semiconductor process to generate corresponding patterns on a semiconductor wafer. A test image of the reticle is provided, and the test image has a plurality of test characteristic values. A baseline image containing an expected pattern of the test image is also provided. The baseline image has a plurality of baseline characteristic values that correspond to the test characteristic values. The test characteristic values are compared to the baseline characteristic values such that a plurality of difference values are calculated for each pair of test and baseline characteristic values. Statistical information is also collected.

US Patent:

6654489, Nov 25, 2003

Filed:

Dec 4, 2002

Appl. No.:

10/314030

Inventors:

James N. Wiley - Menlo Park CA
Jun Ye - Palo Alto CA
David S. Alles - Los Altos CA
Yen-Wen Lu - Los Altos CA
Yu Cao - Sunnyvale CA

Assignee:

KLA-Tencor Technologies Corporation - San Jose CA

International Classification:

G06K 900

US Classification:

382144, 348 87

Abstract:

Disclosed is a method of inspecting a reticle defining a circuit layer pattern that is used within a corresponding semiconductor process to generate corresponding patterns on a semiconductor wafer. A test image of the reticle is provided, and the test image has a plurality of test characteristic values. A baseline image containing an expected pattern of the test image is also provided. The baseline image has a plurality of baseline characteristic values that correspond to the test characteristic values. The test characteristic values are compared to the baseline characteristic values such that a plurality of difference values are calculated for each pair of test and baseline characteristic values. Statistical information is also collected.

US Patent:

7695876, Apr 13, 2010

Filed:

Aug 24, 2006

Appl. No.:

11/466978

Inventors:

Jun Ye - Palo Alto CA, US
Moshe E. Preil - Sunnyvale CA, US
Xun Chen - Palo Alto CA, US
James Wiley - Menlo Park CA, US

Assignee:

Brion Technologies, Inc. - Santa Clara CA

International Classification:

G03F 9/00
G03C 5/00

US Classification:

430 30, 382145, 382147, 382149

Abstract:

A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.

US Patent:

8057967, Nov 15, 2011

Filed:

Feb 23, 2010

Appl. No.:

12/660313

Inventors:

Jun Ye - Palo Alto CA, US
Moshe E. Preil - Sunnyvale CA, US
Xun Chen - Santa Clara CA, US
James Wiley - Menlo Park CA, US

Assignee:

ASML Netherlands B.V. - Veldhoven

International Classification:

G03F 9/00

US Classification:

430 5, 430 30, 382145, 382147, 382149, 257 48

Abstract:

A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.

US Patent:

8318391, Nov 27, 2012

Filed:

Sep 23, 2011

Appl. No.:

13/244218

Inventors:

Jun Ye - Palo Alto CA, US
Moshe E. Preil - Sunnyvale CA, US
Xun Chen - Palo Alto CA, US
James Wiley - Menlo Park CA, US

Assignee:

ASML Netherlands B.V. - Veldhoven

International Classification:

G03F 9/00
G03C 5/00

US Classification:

430 5, 430 30, 382145, 382147, 382149, 257 48

Abstract:

A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.

US Patent:

20050004774, Jan 6, 2005

Filed:

Jul 1, 2004

Appl. No.:

10/883372

Inventors:

William Volk - San Francisco CA, US
James Wiley - Menlo Park CA, US
Sterling Watson - Palo Alto CA, US
Sagar Kekare - Plano TX, US
Carl Hess - Los Altos CA, US
Paul Marella - San Jose CA, US
Sharon McCauley - San Jose CA, US
Ellis Chang - Saratoga CA, US

International Classification:

G01N021/00

US Classification:

702108000

Abstract:

Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.

US Patent:

20110294083, Dec 1, 2011

Filed:

Dec 29, 2009

Appl. No.:

13/142555

Inventors:

James Edwin Wiley - Moraga CA, US
William Akers - Saraland AL, US
William R. Skelding - Sycamore IL, US

Assignee:

TATE & LYLE TECHNOLOGY LIMITED - LONDON

International Classification:

F24J 3/00
B01J 19/00

US Classification:

432 5, 422129, 422187, 422168, 432 1

Abstract:

A molten salt treatment system and process can include one or more tubular conduits flowably connected to a molten salt reactor, the tubular conduit containing concentrically within it a pipe or a shaft separated by an annular space therebetween, and one or more gas sources connected to feed gas into the annular space. The system may include a scrubbing device flowably connected to a molten salt reactor off-gas outlet to receive an off-gas, a first heating device configured to heat the effluent from the scrubbing device, and a filtering device flowably connected to receive the effluent from the heating device. An overflow conduit may be flowably connected to a molten salt reactor overflow outlet to receive molten salt therefrom and discharge the molten salt to a salt recovery vessel, and a blower or other gas mover may be connected to the molten salt reactor and the recovery vessel to prevent backflow of cold gases through the overflow outlet to the molten salt reactor.