James A Wingfield

US Patent:

20230032375, Feb 2, 2023

Filed:

Jul 30, 2021

Appl. No.:

17/390293

Inventors:

- Santa Clara CA, US
Michael L. Golden - Santa Clara CA, US
Sean M. O'Mullan - Austin TX, US
James Wingfield - Austin TX, US
Keith A. Kasprak - Austin TX, US
Russell Schreiber - Austin TX, US
Michael Estlick - Fort Collins CO, US

International Classification:

G06F 11/14
G06F 11/07
G06F 9/30
G06F 9/50

Abstract:

An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of undefective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.

US Patent:

20210407617, Dec 30, 2021

Filed:

Sep 22, 2020

Appl. No.:

17/027983

Inventors:

- Santa Clara CA, US
Keith A. Kasprak - Lakeway TX, US
Vance Threatt - Austin TX, US
James A. Wingfield - Austin TX, US
William A. Halliday - Austin TX, US
Srinivas R. Sathu - McKinney TX, US
Arijit Banerjee - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Santa Clara CA

International Classification:

G11C 29/44
G11C 29/12
G11C 7/12
G06F 12/0811

Abstract:

An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

US Patent:

20140149813, May 29, 2014

Filed:

Nov 28, 2012

Appl. No.:

13/687837

Inventors:

- Sunnyvale CA, US
James A. Wingfield - Austin TX, US
Atchyuth K. Gorti - Austin TX, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G01R 31/3177

US Classification:

714727

Abstract:

A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.