James A Yoder

US Patent:

63298775, Dec 11, 2001

Filed:

Jun 25, 1999

Appl. No.:

9/344756

Inventors:

John Wayne Bowen - Warminster PA
Roger Anthony Fratti - Cumru Township, Berks County PA
James Daniel Yoder - Leola PA

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H03F 368
H03F 360
H03F 304

US Classification:

330124R

Abstract:

There is disclosed a power amplifier includes an in-phase power splitter generating two split signals from an input signal, and two amplifiers capable of operating in different modes. The split signals are provided as respective inputs to the two amplifiers which are coupled through transmission lines such that as the first amplifier approaches the maximum power it can produce, the output from the second amplifier begins to contribute to the power amplifier output and supplements and modifies the power provided by the first amplifier thereby extending the range of input power over which the power amplifier delivers output power.

US Patent:

20140270122, Sep 18, 2014

Filed:

May 30, 2014

Appl. No.:

14/291696

Inventors:

- Allentown PA, US
Harold T. Simmonds - Stewartsville NJ, US
James D. Yoder - Leola PA, US

Assignee:

Agere Systems LLC - Allentown PA

International Classification:

H04M 3/00

US Classification:

379 9306

Abstract:

The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ΣΔ rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.