James Zhebin Yu

US Patent:

7289498, Oct 30, 2007

Filed:

Jun 28, 2002

Appl. No.:

10/187239

Inventors:

James Yu - San Jose CA, US
Mike Morrison - Sunnyvale CA, US
John Rigby - Reading, GB

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H04L 12/28

US Classification:

370389, 711108

Abstract:

A technique for classifying traffic at a network node involves programming a content addressable memory (CAM) array with multiple class-specific entries, where each of the class-specific entries has an associated traffic class, obtaining a protocol-independent key field from an incoming packet, and searching the programmed CAM array with the protocol-independent key field to identify an associated traffic class of the incoming packet. In another embodiment, each of the class-specific entries has an associated traffic distribution policy, which may be applied to an incoming packet.

US Patent:

7333468, Feb 19, 2008

Filed:

May 16, 2005

Appl. No.:

11/129798

Inventors:

Sebastian Turullols - Los Altos CA, US
Aly E. Orady - Sunnyvale CA, US
James J. Yu - San Jose CA, US
Andrew C. Yang - Sunnyvale CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04J 3/24
H04J 3/06
H04L 12/56
H04L 7/00
H04L 7/04
H04L 9/00
H04B 1/18
H04B 1/10

US Classification:

370349, 370350, 37039562, 370509, 370514, 4551803, 4551811, 4551832, 375357, 375366, 375362, 375350, 375355, 713178

Abstract:

A packet stream multiplexer may include one or more control loops (e. g. , digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated timestamp to zero. A second control loop may more quickly drive a first derivative of the error to zero. The second control loop may include a set of digital filters ordered according to tracking speed. The output of the slowest filter is initially selected for updating the source clock frequency estimate. As time progresses, the faster filters are selected in succession. The estimated source clock frequency is used to restamp packets of the packet stream as they are sent out onto an output channel.

US Patent:

7696765, Apr 13, 2010

Filed:

Sep 3, 2007

Appl. No.:

11/849336

Inventors:

James Yu - San Jose CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G01R 27/02
G06F 1/26

US Classification:

324722, 324713, 713300

Abstract:

A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port.

US Patent:

7738498, Jun 15, 2010

Filed:

Aug 9, 2005

Appl. No.:

11/199627

Inventors:

James J. Yu - San Jose CA, US
Andrew C. Yang - Sunnyvale CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H04J 3/06

US Classification:

370503, 375376, 375215

Abstract:

A system including a memory (storing a set of data records), a digital phase-locked loop (PLL) and digital circuitry. Each of the data records is allocated to one packet stream in a set of packet streams. The digital circuitry is configured to: invoke a read operation from the memory in response to a received stream indicator and received channel indicator corresponding to a current timestamp-bearing packet; generate an output timestamp for the current packet equal to an expected timestamp provided by the memory as part of the read operation; and generate error data based on argument data including a received input timestamp, a received slot delay value, a previous source frequency estimate and an expected timestamp provided as part of the read operation. The digital PLL is configured to compute an updated source frequency estimate based on information including the error data and the previous source frequency estimate.

US Patent:

7764717, Jul 27, 2010

Filed:

May 6, 2005

Appl. No.:

11/123820

Inventors:

James J. Yu - San Jose CA, US
Sebastian Turullols - Los Altos CA, US
Aly E. Orady - Sunnyvale CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H04J 3/02

US Classification:

370537, 370271

Abstract:

A multiplexing system having an input unit, a storage unit and control unit. The input unit receives data units corresponding to multiple source data streams and extracts packets from the data units. The control unit computes data rate estimates for the source data streams based on timestamps in the source data streams. The storage unit stores a packet count and previous timestamp value for each source data stream. The control unit computes a preliminary data rate estimate for a source data stream based on samples of a local clock if timestamps are not received promptly. The control unit also computes scheduling rates based on the data rate estimates. The scheduling rates are used to control the rates of allocation of data from the source data streams into a multiplexed output stream. The control unit computes scheduling rates in a way that avoids oversubscription of the output channel.

US Patent:

7912082, Mar 22, 2011

Filed:

Jun 9, 2008

Appl. No.:

12/135348

Inventors:

Andrew C. Yang - Sunnyvale CA, US
James J. Yu - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

H04L 12/66

US Classification:

370463

Abstract:

A system includes one or more processing units coupled to a network interface unit. The network interface unit may include a network port for connection to a network and a virtual interface that may be configured to distribute an available communication bandwidth of the network port between the one or more processing units. The network port may include a shared media access control (MAC) unit. The virtual interface may include a plurality of processing unit resources each associated with a respective one of the one or more processing units. Each of the processing unit resources may include an I/O interface unit coupled to a respective one of the one or more processing units via an I/O interconnect, and an independent programmable virtual MAC unit that is programmably configured by the respective one of the one or more processing units. The virtual interface may also include a receive datapath and a transmit datapath that are coupled between and shared by the plurality of processing unit resources and the network port.

US Patent:

7956616, Jun 7, 2011

Filed:

Mar 29, 2010

Appl. No.:

12/749489

Inventors:

James Yu - San Jose CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G01R 31/08

US Classification:

324525, 324522, 324713, 713300

Abstract:

A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port.

US Patent:

8031731, Oct 4, 2011

Filed:

Jun 9, 2008

Appl. No.:

12/135368

Inventors:

James J. Yu - San Jose CA, US
Andrew C. Yang - Sunnyvale CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

H04L 12/66

US Classification:

370419, 370463

Abstract:

A system for sharing a network port of a network interface includes a plurality of processing units, a first network interface unit coupled to a first portion of the plurality of processing units, a second network interface unit coupled to a different portion of the plurality of processing units, and a link coupled between the first and second network interface units. The first and second network interface units each includes an independently controllable network port for connection to a network, and a virtual interface. The network port includes a shared MAC unit, a link interface, and control logic, which may selectably route packets between processing units of the first portion of the plurality of processing units and the network via the link and the network port of the second network interface unit. The virtual interface may include a plurality of independent programmable virtual MAC units.

Address:

14619 Eastern Redbud Ln, Houston, TX 77044

Phone:

2815439981

VIN:

5TDYK3DC3CS214971

Make:

TOYOTA

Model:

SIENNA

Year:

2012